RISC-V Verification: From Simulation To Formal

Assessing all possible firings of an instruction, along with those before and after.

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Axiomise’s Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all the bugs in a design and how formal verification can help with bug hunting for corner-case bugs and exhaustive proofs of bug absence.



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