Risk Vs. Reward

One of the most persistent business myths is that deep pockets in challenging times always win in the end. While that has proven a successful model in many industries where the barrier to entry is enormous and rising, in the technology world the outcome isn’t always what you’d expect even with those same variables.

In fact, the history of technology is littered with former business giants who thought they could outlast, underprice, out-sue or simply block their competition. They were wrong. Nimbleness, good ideas and real value always seem to come through. Tesla, Google, Amazon and the resurgence of Apple with, of all things, an MP3 player, all attest to that.

On the manufacturing and materials side, this emphasis on new and better has been closely associated with Moore’s Law. Some proponents claim that Moore’s Law is an economic observation. Others claim it’s a technology statement. The reality is that it has always been a slice of both, and breaking them apart has been difficult because the economics and the technology have been so tightly coupled in the past. As we move into the world of triple and quadruple patterning, with new materials, new methodologies and soaring costs, the economics no longer will be moving in lock step with the technology.

While the foundry model has democratized the exorbitant investment in equipment and process technology needed to manufacture chips, the price tag continues to rise rapidly. It costs more to model, design, integrate, verify and tape out a chip, and it costs more to develop the masks and to manufacture it. Swapping to 450mm wafer sizes may help, if the tools to handle the larger wafers are developed in time, with sufficient yields and manageable testing approaches.

For the first time, executives across the semiconductor ecosystem are beginning to talk about value. Top executives at multiple companies have given speeches over the past year where they insist that consumers are willing to pay more for greater value, meaning more complex chips with more functionality, better performance and longer battery life. That may be true in some markets. It will not be true in others.

What is clear, though, is that not all technology will be moving forward at the same pace and in the same way as it did in the past. FinFETs are a technological leap, but they’re harder to design and more expensive to manufacture. While they reduce current leakage, power densities continue to rise at advanced nodes, creating new issues that have to be dealt with. New materials help, but they’re more expensive and harder to work with. Defect density increases, because what used to be a blemish at 32nm is suddenly a chip-killing defect at 16nm. Just being able to spot defects at the most advanced nodes requires new metrology equipment, and on a 450mm wafer that may be even tougher to keep pace with.

Lithography has its own well-publicized list of delays. EUV was supposed to go live at 45nm. It’s now looking like a stretch to say it will be ready for 7nm with commercially acceptable throughput. That means quadruple and maybe quintuple patterning, if suitable alternatives aren’t found.

It’s not that engineers and materials scientists can’t build advanced chips and solve all of these problems. But some serious questions are beginning to surface about whether that money is better spent moving from one feature shrink to the next, or whether it should be applied at existing nodes for significantly longer periods of time—possibly using new architectures, packaging approaches and business models to improve throughput, lower resistance (and power), and build on commercially available platforms using logic and memory subsystems.

The semiconductor industry has come to a fork in the road, and the future will be defined by which companies choose which paths—or some combination of both—and which ones steadfastly maintain their course. There are a lot of uncertainties on all sides, and those left standing at the end of this shift will either have even deeper pockets or no pockets at all.