See The Internet Of Things…In 3D

No, you don’t need 3D glasses to experience two of the hottest emerging technology trends in electronics — just take advantage of the longest running conference series on the topic of 3-D integrated circuits. Now in its 11th year, the 3D Architectures for Semiconductor Integration and Packaging conference will take place in San Francisco next week. The event will feature two pre-conference symposiums, one on 2.5/3D-IC design tools and flows, and another on 3D integration process technology. This conference spans the entire ecosystem, from technology developers and equipment suppliers to EDA and end-user designers.

This year, I have the honor of delivering the keynote address titled, “A Design Ecosystem for Internet of Things, How 3D-IC Standards will Enable a New Growth Paradigm”. Although 3D integrated circuits (3D-ICs) have long been anticipated as the major emerging alternative to classical process scaling, the coming wave of devices driving the Internet of Things (IoT) era will mandate a new set of integration requirements that only 3D-ICs can properly satisfy.

The need to integrate a wide range of functionality — spanning digital, memory, analog, RF, MEMS, sensors, and energy harvesters — cannot be economically addressed exclusively with single-die solutions. Yet the challenges also extend into new design methodologies supporting extreme low power operation, custom packaging co-design and optimization, and including system-level interfaces with embedded software and big data analytics. By analyzing the characteristics of upcoming growth market categories from the system level, we can assess the changing design methodologies required and, from that, infer the new types of design data exchanges needed to support cost-effective design involving 3D-ICs.

Most industry analysts are anticipating that 3D-IC design eventually will become the best long-term solution to address increasing requirements in size, power, performance, and diverse range of IP content. Standards will be essential to support this ecosystem, and Si2’s Open3D Technical Advisory Board (TAB) has already delivered several key design flow standards with a third standard on the way.

To best capture the next set of needs to support the 3D design environment, the Open3D TAB is preparing a 3D-IC Survey to capture up-to-date user requirements and plans for interposer and 3D-IC designs — to fine-tune Si2’s 3D-IC strategy for 2015 and beyond. Deploying a user friendly and anonymous survey, Si2 will capture within 10 to 15 minutes many companies’ current activities, plans, questions and challenges in this strategic technology segment. If you are an EDA or System/IC design expert and experienced or interested in this field, please email [email protected] if you have not yet already been invited to contribute your expertise to this survey.

The 3D Architectures for Semiconductor Integration and Packaging Conference (3D ASIP) and symposiums will be held Dec. 10-12, 2014, at the Hyatt Regency San Francisco Airport, in Burlingame California, organized by RTI International (register at www.3dasip.org). To learn more about Si2 and the Open3D TAB, please visit Si2 (www.si2.org).