Shock Value

By Norman Chang
Chip-Package-System (CPS) ESD simulation enables system-wide ESD robustness validation, a common challenge in automotive and aerospace applications.

To enable CPS ESD analysis requires an accurate chip electrostatic discharge (ESD) model and a comprehensive system-level ESD methodology. Using an accurate ESD chip model provides the following three benefits. First it helps determine the chip pins voltage/current over time and provide a realistic view of the CPS ESD prior to hardware availability. The second benefit is to perform the diagnosis of potential failure mechanisms when a CPS ESD failure occurs. Realistic chip modeling furnishes the designer with accurate V(t) and I(t) on the chip pins, and once the V(t) and I(t) are obtained on the chip pads, a chip-level ESD static or dynamic simulation can subsequently be performed. The third advantage is in using the model to help verify fixed solution robustness by comparing pre-/post-fix voltage/current values on the chip(s) pins with hard or soft failures. Together these benefits can help identify CPS ESD design weaknesses and increase overall product yield — from early prototyping all the way to sign-off — which is great, but how does it work?

Chip ESD Compact Model
A Chip ESD Compact Model (CECM) is an accurate compact representation of a die containing a passive RC(L) model, the current signature of ports for a specific scenario, and optional ESD protection elements such as diodes and RC-based clamps.

In CECM, the total capacitance (Cdie) of a power/ground domain pair includes the power/ground coupled capacitance, intentional decap, device intrinsic capacitance, and non-switching cell capacitance and their loads. The CECM connected with a package/board netlist can achieve the same port response as detailed die and package/board co-analysis.

Using CECM for PCB ESD Prediction and System ESD Validation
A CPS ESD simulation using CECM without on-chip ESD protection elements can enable a better understanding of the PCB ESD protection effectiveness. When a PCB is zapped in this scenario, the energy will propagate through the connector, PCB trace, and on-board ESD protection elements, and can highlight V(t) and I(t) on the chip pins that exceed the acceptable voltage and/or current limits. This simulation helps reveal the weaknesses in the PCB power/ground/signal layout, or the need for extra PCB ESD protection elements. The example below demonstrates how using a CECM without an on-chip ESD protection element for different Cdie, results in a wide range of V(t) at the chip pin.

Running a CPS ESD simulation with CECM that includes on-chip ESD protection elements provides a realistic V(t) and I(t) of the chip pins. The modeling of on-chip ESD protection helps validate that the system meets IEC61000-4-2 requirements.

Full-chip Diagnosis and Predictive Simulation
Using a comprehensive CPS ESD simulation methodology with an accurate Chip ESD Compact Model enables diagnosis and predictive simulation of PCB ESD discharging events and exhaustive analysis of the chip, package and board ESD protection, highlighting weaknesses in the design that can be susceptible to failure caused by an ESD event. By implementing integrated modeling, extraction, and simulation capabilities from early prototyping to sign-off, designers can successfully identify the most vulnerable area of the design, meet ESD guidelines, and improve product yield.