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Signoff-Accurate Partial Layout Extraction And Early Simulation

See the effect of layout while the layout is still in progress.

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It is a rewarding experience for EDA developers and users to collaborate on deploying advanced techniques to improve design productivity. This blog will describe the experience of collaborating with customers on a new technology for reducing the number of analog design iterations. Analog design requires that engineers balance the needs to 1) reach market quickly 2) deliver high quality 3) at low cost. To achieve all three, they need to be creative.

One creative way designers are meeting these goals is by deploying a Partial Layout Extraction (PLE) and early simulation flow. This flow helps catch potential electrical issues early in the design cycle, which reduces the time designers need to spend on achieving analog design closure. The PLE flow provides designers with the ability to do accurate simulations using parasitics extracted from a partially completed layout. In this way, they can evaluate the impact of parasitic and layout dependent effects on their designs while the layout is still being finalized.

What is Partial Layout Extraction (PLE) flow and why it is needed?

There are see three main challenges facing analog design teams today:

  1. More simulation workload, due to variability and reliability
  2. More design iterations, due to impact of physical effects
  3. More layout effort, due to increasing complexity of process technologies

Fig. 1: Challenges faced by analog design teams.

Analog designers run simulations to ensure that their designs work as expected after layout. Often, they find issues on the first iteration of the layout because of the impact of layout dependent effects and parasitics in the layout. Often these parasitics in the completed layout are very different from the original estimates in the schematic. It takes a long time to finish a layout, so finding these issues only after the layout is completed adds a lot of time to the design cycle. And it takes many iterations to finally converge the layout to meet performance targets.

Synopsys Custom Compiler’s Partial Layout Extraction (PLE) enables early simulation with accurate parasitics by using Foundry-qualified sign-off engines. This helps reduce the time spent in iterations between design and layout.

In the Synopsys Custom Compiler PLE flow, StarRC and IC Validator are used to extract the parasitics and LDE effects. By using signoff engines, rather than an approximation built into the layout tool, the Custom Compiler PLE flow ensures accuracy and quality of the results. Results that don’t correlate with signoff risk sending designers on a wild goose chase!

Fig. 2: Partial layout extraction (PLE) and early simulation flow.

Using PLE Flow with Foundry IPs

For one of Synopsys’ key customers, the PLE flow helped to avoid long iteration cycles vs. their traditional design flow. This customer evaluated the flow with various type of analog blocks on the latest advanced nodes.

Fig. 3: Traditional vs. PLE-based analog design flow.

During the evaluation, they could literally see the major shift from “long wait for layout parasitic netlist” to “partial layout netlist with best available parasitics,” which designers were able to simulate quickly and see the effect of layout when the layout is still in progress.

To show an example, here are the results from a 7nm test case highly susceptible to layout parasitics. The designer was able to quickly place a critical sub-block of the layout with no routing and generate the simulation-ready netlist to see the effect, and then he would ask the layout designer to do the critical routing between the blocks and see the progression of results with the clear visibility on the parasitic effects of layout in progress.

In this example, the designer could get parasitic simulation results in two hours that were within 5% of the final layout – saving at least a full week of layout time per iteration.

Fig. 4: Results from Custom Compiler’s PLE flow on example design.

Custom Compiler’s PLE flow is a proven differentiating technology and a clear productivity booster for analog design teams. Our customers can tape-out their designs much more quickly with high quality and low cost.

To learn about how our Custom Compiler users are benefiting from PLE, you can watch Samsung’s SNUG Silicon Valley 2022 video. The full video is available on-demand at Synopsys Learning Center at SolvNetPlus. Or check out the website for our Synopsys Custom Design Family, which includes Custom Compiler design and layout, PrimeSim circuit simulation, StarRC signoff parasitic extraction and IC Validator physical verification.



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