Smart Plug-And-Play DFT For Arm Cores

Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ATPG that effectively reduce DFT effort, minimize ATPG runtime, and still achieve the target test coverage. Hierarchical DFT enables designing and testing of these designs in a systematic and repeatable manner.

A true hierarchical DFT methodology divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. The flow includes creating graybox views—lightweight models that only include wrapper chains, which isolate the core logic. In Figure 1, the image on the left shows a top-level flat ATPG in which the entire SoC must be tested together. The image on the right illustrates hierarchical ATPG, with each block isolated for test by a wrapper chain. Each core can be tested independently of each other and of the top level. The test access mechanism (TAM) is used to maximize channel/pin bandwidth to whichever blocks are being tested. The hierarchical implementation requires fewer chip pins, reduces the test memory footprint and ATPG runtime.

Figure 1: Flat vs Hierarchical DFT

Another distinct benefit of hierarchical DFT is that ATPG does not require a final full-chip netlist; you can perform all DFT including test pattern generation for blocks as they become available. Core-level patterns are retargeted to the top-level design, with graybox models used to provide a lightweight netlist for interconnect test between core wrapper chains. For testing top-level logic, only the netlist for top-level logic and interconnect between cores is needed to create test patterns.

A true hierarchical DFT methodology is based on a smart plug-n-play infrastructure as a foundation and has the following characteristics:

• Complete DFT and ATPG in an integrated test platform
• Automatically reuse and mapping all core-level DFT and core initialization to the chip top level
• 10x faster ATPG runtime and 10x less computation resource
• IEEE standard 1687/IJTAG flow

Adopting a hierarchical DFT flow is easier than ever since Arm and Mentor created an RTL-based, hierarchical DFT reference flow. This DFT flow provides a simple and verified hierarchical test methodology for cost-effective, high-quality test of Arm IP, making it easier to reap the benefits of hierarchical DFT. The flow defines all the steps necessary to implement RTL-level hierarchical DFT, taking advantage of built-in automation, and includes scripts, interfaces, and documentation.

In this flow, two levels of DFT were implemented based on logic distribution of the design. It demonstrates hierarchical DFT for wrapped Arm Cortex-A75 cores and a top level. Any similar type of subsystem with Arm cores can refer to this flow. The reference flow contains memory BIST (built-in-self-test), IEEE 1149.1 boundary, on-chip clock controller (OCC), embedded pattern compression, and a flexible test access mechanism (TAM) for the best channel resource utilization. All DFT was inserted using Mentor’s Tessent family of tools. A diagram of the design with all DFT logic inserted is shown in Figure 2.

Figure 2: Overview of DFT inserted design.

The detailed flow is based on a test case as a bottom-up flow that starts with core-level RTL design (Figure 3). It takes you through every step with images showing the results of each step from core-level DFT to chip-level DFT.

Figure 3: Flow chart of all reference test case DFT steps.

The bottom-up flow starts with memory BIST insertion in the Arm A75 core, followed by embedded test compression (EDT) and OCC insertion, all at RTL. Within the A75 core, the Tessent MBIST was implemented for Arm’s shared bus memory. Because there are four identical A75 cores in this reference design, we can broadcast input test data to them. After DFT insertion, core-level synthesis is performed as usual. Next is scan insertion and retargetable ATPG for the core is performed. Once core-level test is done, the reference flow moves on to the top-level design.

Top-level DFT insertion includes the following:

• A JTAG compatible TAP controller
• Boundary scan logic
• MBIST assembly module for shared bus memories in the chip top level
• IJTAG-based MBIST for individual memories are inserted

All these test instruments were easily defined using the DFT specification method, an automatic hardware generation method that offers smart default DFT based on understanding of design. It also provides the maximum flexibility for power users.

A second DFT insertion pass adds EDT logic and OCCs. The table below shows the scan configuration of core and top level.

Based on the scan configuration, a TAM was added that can utilize and optimize the precious test channels on the chip. Corresponding retargeting modes were defined during this second pass during scan insertion. It also helps to plan early on the scan configuration, as done in this example, knowing global available resources.

This flow is automated with a unified database that shares all DFT information to every DFT tool hosted on the database. During the next step, pattern generation, the platform will recognize and understand what DFT exists and provide smart configurations based on this understanding.

The following table shows the chip top-level ATPG results.

* Shows results at 97.13% baseline coverage.

** Shows results that regard subsystem as physical level, without boundary scan’s coverage loss.

This Arm-Mentor hierarchical DFT reference flow provides a simple and verified test methodology for an SoC containing Arm IP. It also shows the value of the partnerships and ecosystem between IP and EDA providers that helps customer to achieve cost-effective, high-quality DFT. Learn more in our whitepaper, Tessent Hierarchical ATPG Reference Flow for Arm Cortex-A75.