How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.
A presentation discussing how RedHawk enables physical design weakness identification, automatic repair the source of the supply noise, analyze impact of dynamic voltage drop on timing and jitter, verify power and signal EM, and provide a model of the chip’s PDN for system-level analysis.
To view this video tutorial, click here.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
Pitches continue to decrease, but new tooling and technologies are required.
Buried features and re-entrant geometries drive application-specific metrology solutions.
Issues involving design, manufacturing, packaging, and observability all need to be solved before this approach goes mainstream for many applications.
Etching tools are becoming more application-specific, with each new node requiring higher selectivity.
Existing tools can be used for RISC-V, but they may not be the most effective or efficient. What else is needed?
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Technical and business challenges persist, but momentum is building.
Gate-all-around is set to replace finFET, but it brings its own set of challenges and unknowns.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
High speed and low heat make this technology essential, but it’s extremely complex and talent is hard to find and train.
The industry seems to think it is a real goal for the open instruction set architecture.
Leave a Reply