SoC Power Integrity And Sign-Off For 28nm Designs

How to identify design weaknesses, automatically repair the supply noise source, analyze the impact of dynamic voltage drop and verify power and signal EM.


A presentation discussing how RedHawk enables physical design weakness identification, automatic repair the source of the supply noise, analyze impact of dynamic voltage drop on timing and jitter, verify power and signal EM, and provide a model of the chip’s PDN for system-level analysis.

To view this video tutorial, click here.

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