Sprint To The Finish Line

By Ed Sperling
Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation.

LPHP: How important is it to be at the front end of Moore’s Law?
Hsu: Strategically, it’s important for us to be ahead of the industry. If the process nodes were to stop today, who will win? The first one to the market has the advantage. We’re very conscientious about that.

LPHP: The dynamics of moving to the next node are changing, though. Companies are staying at some nodes longer, and then skipping nodes. How does that affect Cadence?
Hsu: They may jump to whatever makes sense for them, but our licenses are increasing.

LPHP: Is that because of complexity or more companies moving forward?
Hsu: It’s driven by complexity.

LPHP: So even within the same company you have more licensees, right?
Hsu: That’s correct. They also buy more companies. Our material business model is still license counts, and it’s growing. The industry has matured. They know this is an investment for the future. When that happens, EDA becomes healthier. Our license average is now about 2.6 years, according to our financial reports. It used to be 4 years or 6 years. With this change, we can invest more intelligently in the future. We can look at what is the right thing to do.

LPHP: What does Cadence view as the right thing to do?
Hsu: If you look at the IC market, one side was digital and the other was analog. Then the digital part started to bifurcate because there is commodity digital and high-end, advanced node digital. There is one part of the market that moves to the next node whenever it’s possible. The others either got bought by the big digital companies because it was hard to differentiate, or they became IP companies. What’s interesting is the analog/RF companies now want to use digital techniques or incorporate more digital parts. So now there is a new market in the middle, which is traditional digital plus analog. We’re calling this high-performance mixed signal. We believe this will be a very successful market.

LPHP: How do you assess the potential of markets?
Hsu: The way we look at a market at Cadence is we squarely focus on the street. What do they really need to be successful? In 2005 and 2006 we started a Power Forward Initiative to focus on low power design. We have very streamlined and mature automation. In 2009, we started digital-enabled mixed signal. Low-power is ubiquitous now. It doesn’t just apply to advanced nodes, which it did initially. But in the analog world people do a lot of those things manually. Digital needs tremendous automation. And the reality is those worlds do connect. So we started the Digital/Mixed-Signal Initiative about 3-1/2 years ago, with the idea that down the road low power would merge with mixed signal. That direction, plus full custom plus high-end digital, are where we are focused.

LPHP: What happens with software? It’s bloated, energy inefficient, and the tools to improve software don’t exist yet.
Hsu: We’re a software company and we know how terrible it can get. Mature companies learn this. New companies have a tougher time, because software is a team sport. Inside of Cadence, we initiated some changes to improve quality.

LPHP: How do you define quality in software?
Hsu: There are different aspects to that. It’s not just writing the code so it works.

LPHP: But things like power and efficiency have never been major considerations in software, right?
Hsu: A lot of it involves efficient software profiling. When you look at software, how do you develop solid software? If you go into real low-power design, what’s the power consumption? And if you want to achieve certain things from an energy perspective, you have to reduce it further and further. It’s an optimization problem. In the last 12 months we did so much optimization in our tools. In some cases we’ve done 3,000 or 4,000 times better. A lot of it has to do with tuning it to new process technology coming on line.

LPHP: How much of this optimization can be done through clock synchronization?
Hsu: That’s the traditional way of doing things, but today we purposely make the clocks not in sync. This is adapted to the data. There are as many as 500,000 clocks. With the variability of all the buffers, how do you calculate it accurately enough so the logic still comes out right? And then you have to minimize power and frequency. Now you’ve opened another dimension and the challenge is huge. As an industry, how can you do an SoC design with the least amount of risk and cost?

LPHP: There aren’t that many acquisition targets left. What does that do to your acquisition vs. grow everything internally strategy?
Hsu: From a tools standpoint, there’s a change. There is dramatically less for us to acquire. This is why in 2009 we started more than 20 projects. About 18 months ago we saw the industry changing where we would be fighting fiercely on all fronts against only Synopsys. Just for my team we hired more than 90 people who were well known in the industry.

LPHP: Are you seeing a shortage of those kinds of people?
Hsu: There are absolutely fewer of them because there are fewer people coming out of school. Increasingly, this industry is about physics and math, so there aren’t as many people coming out. That’s one of the reasons we hooked up with universities to set up intern programs.