I’m in a great position to hear lots of interesting opinions about technology today and this week was no different. During a discussion with Atrenta CTO Bernard Murphy about power and performance tradeoffs, he mentioned that he is not hearing a lot of engineering teams using DVFS (dynamic voltage and frequency scaling) because it creates complications for clock synchronization and makes the d... » read more

Sprint To The Finish Line

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: How important is it to be at the front end of Moore’s Law? Hsu: Strategically, it’... » read more