Is DVFS worth applying in traditional bulk CMOS?


I’m in a great position to hear lots of interesting opinions about technology today and this week was no different. During a discussion with Atrenta CTO Bernard Murphy about power and performance tradeoffs, he mentioned that he is not hearing a lot of engineering teams using DVFS (dynamic voltage and frequency scaling) because it creates complications for clock synchronization and makes the design much more complex to verify. He said the general view seems to be it’s not worth it – there are better ways to save power.

Even among some of the biggest smartphone players this holds true.

“In principle,” Murphy said, “you could save more power, but the added complexity and verification is significant.”

This was rather surprising to me until I spoke with David Jaquet, principal engineer at STMicroelectronics who said that ST uses a lot of DVFS…because they are on the FD-SOI process, which makes all the difference. This has allowed ST to create CPUs running at 0.6volt going up to 1.2 or 1.3volts.

Jacquet said DVFS is more limited in bulk technology, which explains Dr. Murphy’s comments above. “In FD-SOI, you can really do a very wide DVFS because you have body bias so you can really play with both and of course the characteristic of the process and the control of the transistor is better in FD-SOI.”

He also noted that what is emerging even in server applications and other markets is that a lot of processing power is needed but not all the time. “In some cases you may need a much lower processing power and what people are trying to achieve is that you only pay for this extra processing power when you need it. The challenge is to design systems that can go very fast like a car that could go to 200km but at the same time people want the car to be able to run at 4km without consuming much more than what it should be…with DVFS we can really run very fast up to 3GHz but the same CPU can run in a very low power mode when it’s needed. The only way to achieve that is to use the DVFS.”

Giorgio Cesana, marketing and communications director for ST’s R&D department explained further that the problem with traditional technologies is that as soon as you go in underdrive conditions with a power supply which is well below the nominal voltage, the loss of performance is dramatic so the usable supply range for providing the correct supply for the device is very limited.

“If you look at some other implementations, even the people that use DVFS use a very limited voltage range because FD-SOI is a fully depleted technology this allows the transistor to have very good electrostatic control and excellent performances even in underdrive conditions. This is making FD-SOI appealing for lowering as much as possible the power supply still with interesting performances.”

What’s your experience with DVFS? Chime in below with your comments!

~Ann Steffora Mutschler

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