Squeezing Out More Test Compression

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been quite effective at containing test costs. For many designs, standard test compressions is enough, but ICs for use in automotive and medical devices require a higher manufacturing test quality, which translates to more test patterns and longer test times. These factors lead directly to increased test costs. These types of designs need to employ additional DFT technologies.

One way to reduce pattern count through increased efficiency of DFT is to use a hybrid ATPG/logic built-in self-test (LBIST) method. This technique has gained increased adoption among automotive IC designers. The once-separate ATPG and LBIST technologies have merged so the scan compression IP can also apply BIST tests. Another method of reducing test pattern count has been through the use of test points. However, traditional test points didn’t target both scan compression and BIST.

There are test points that work with a hybrid ATPG/LBIST methodology, and it turns out that they work more efficiently than test points for either EDT or BIST separately. The test points that target both scan compression and BIST cut test time and cost significantly with no loss of test coverage.

Why use Hybrid ATPG/LBIST?
The standard method of manufacturing test has relied on embedded ATPG compression for many years. To get higher coverage and in-system test for mission-critical automotive ICs, logic BIST (LBIST) is used. Whereas scan test applies deterministic stimulus, LBIST applies pseudo-random patterns to the circuit. LBIST responses are collected in a Multi-Input Signature Register (MISR), which requires the circuit to be “X-free,” meaning that no unknown values are observed. You achieve X-free design by controlling the propagation of random or unknown data from sources within a circuit. LBIST is great for in-system test because the generation of patterns and collecting of signatures is fully located on-chip. The downside is that it may take a large number of patterns, and a relatively long amount of time, to reach the required coverage goals.

ATPG excels in high-defect detection for stuck-at and transition delay tests, including specialized fault models including timing-aware, cell-aware, path delay, and bridging faults. ATPG delivers the high-quality manufacturing test required for automotive ICs, but it also presents challenges in the form of large test pattern sets that drive up test costs and time.

So, why not use both these approaches to cover test of automotive IC designs in various scenarios: wafer, packaged, and in-system? There are a couple of reasons. One, the chip area required for both the LBIST LFSR (linear feedback shift register) and the compression decompressor for ATPG. They have always used different logic, even though their functional purposes are similar.

That’s where this hybrid ATPG/LBIST approach comes in. You can combine the logic from embedded compression ATPG and LBIST without the area penalty. The hybrid ATPG/LBIST strategy has become widely used by designers of automotive ICs. Figure 1 illustrates the combined logic architecture of hybrid TK/LBIST.

Figure 1. The logic architecture of Mentor’s Tessent TestKompress TK/LBIST, a hybrid ATPG/LBIST solution, with test points.

Efficiency plus test points
The question arose: how can we make hybrid ATPG/LBIST even more efficient? One place to look was test points, which are dedicated design structures used to improve the test results for LBIST and for ATPG. Traditional LBIST test points (Figure 2) improve results by breaking up areas within the circuit that are random-pattern resistant, such as large blocks of logic focused on encoding or decoding.

Figure 2. BIST test points are good at random pattern coverage, but not so good for reducing pattern count in ATPG mode.

Test points targeted for ATPG pattern count reduction do so by letting parallel logic cones share the same ATPG patterns. These test points help to control growing vector counts by reducing the number of vectors needed for the same original coverage. Test points targeting pattern count reduction typically reduce pattern count by 2-4X beyond what is achieved with on-chip compression alone.

Figure 3 illustrates an EDT test point circuit. Suppose T₁ test patterns are needed to detect faults propagating to gate G3, so the other input must be set to 1. Setting this node to 1 precludes the detection of faults propagating through G4. Likewise, setting the other input of gate G4 to 0 blocks propagation of faults through G3. Because faults in both groups cannot be detected by the same test patterns, the total number of test patterns is T1 + T2.  This can be resolved so that detection of faults propagating to both gates can be detected by inserting an EDT test point on one of the stem branches. For example, a test point on the left branch achieves independent 1-controllability of this line; a test point on the right branch allows 0-controllability of that line. The number of test patterns then becomes equal to max{T1 , T2}. If T1 ≈ T2, you suddenly have cut pattern count in half.

Figure 3. EDT test points are good at reducing pattern count.

But neither ATPG nor BIST test points are individually suited for use in a hybrid ATPG/BIST environment. The two types of test points can still be used in a hybrid ATPG/BIST environment, but it requires running two separate test point insertion runs.

This issue was solved by developing a newer hybrid test point technology that combines and improves upon previous test point algorithms. These hybrid test points improve ATPG compression as well as random pattern coverage beyond what each separate test point can achieve. Plus, they are inserted in a single pass, which streamlines the design flow.

How do Hybrid ATPG/LBIST test points work?
The hybrid ATPG/LBIST test point technology combines all the benefits of EDT and LBIST test points and works better than either type of test point separately. It combines the co-targeting of multiple test point goals (pattern count reduction and BIST coverage) with more advanced test point analysis and insertion algorithms. For an automotive IC, hybrid test points deliver better in-system test coverage, which is important for meeting with the ISO26262 requirements. If your design doesn’t need better LBIST stuck-at coverage, then the hybrid test points can maintain coverage with up to 10x fewer LBIST patterns.

The results based on these new test points are better than the sum of both previous test points in many cases. Table 1 shows the improvement in test coverage with hybrid test points over EDT or LBIST test points separately. The average test coverage improvement between LBIST and hybrid test points is 3.25%.

Table 1. LBIST test coverage (TC) improvement for three different test points. Mentor’s new VersaPoint Hybrid ATPG/LBIST test points outperform either EDT or LBIST test points for test coverage.

Hybrid test points are also better than EDT test points at reducing ATPG pattern count. Table 2 illustrates.

Table 2.  Comparison of ATPG pattern count with three types of test points. The ATPG baseline columns show the test coverage (TC) and pattern count (PC) with no test points inserted. The ATPG PC @baseline TC columns show the pattern counts for each of three test point types, with the same test coverage at baseline. The red-outlined columns calculate the difference between baseline PC and PC with each of three test point types. Hybrid ATPG/LBIST test points outperform either EDT or LBIST test points for pattern count reduction.

Hybrid test points are in use at serveral large semiconductor companies as a replacement for separate LBIST and ATPG test point insertion in their hybrid ATPG/LBIST testing strategies. The technology has been used on automotive ICs to address safety-critical test requirements in order to reach Automotive Safety Integrity Level (ASIL) C and D certification.

Hybrid ATPG/LBIST test points reduce deterministic test pattern counts and improve random testability, and the insertion algorithm is much faster than previous algorithms.

For more information, download our whitepaper, Improving Test Pattern Compression with Tessent VersaPoint Test Point Technology.