Stacked Dies Gain Attention, But So Far Little Traction

Market adoption hinges on development of multiple types of through-silicon vias, standards, cost and market readiness.

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By Ed Sperling

For the better part of two decades there has been a steady stream of predictions about the abrupt end of Moore’s Law, but it now appears the formula for doubling the number of transistors on a die every couple years will simply dissipate rather than fall off a cliff.

While companies such as Intel and IBM continue to develop road maps that extend their road maps all the way to 11nm and 7nm, respectively—at least carrying development through the end of the next decade—the reality is that SoCs will likely contain components built using multiple process nodes. There will undoubtedly continue to be development at the most advanced nodes, but there also will be some components that reach back to 130nm, and some all the way to 180nm.

“At some point Moore’s Law runs out of steam and there will be a crossover to different approaches,” said Charlie Janac, CEO of Arteris. “You can make 11nm steppers and do physical vapor deposition, but they’re going to be very pricey.”

Developers and chipmakers say economics already make stacked die viable. Now it’s just a matter of putting all the pieces in place to make it technologically possible.

Texas Instruments, for one, is looking at a number of different integration models including vertical integration using through-silicon vias (TSVs), said Robert Tolbert, TI’s OMAP platform marketing manager.

“When you have a chip that includes wireless, LAN connectivity, Bluetooth and GPS (global positioning systems), all of those technologies have to be integrated with each other,” Tolbert said. “Through-silicon vias are one approach we are looking at. There also has to be more integration at the package level.”

The stacked die approach
TI isn’t the only company looking at stacked die as a potential solution. All the major chip developers are. In fact, the standards group Si2 currently is working to develop standards for 3D stacking, which should speed its adoption once those standards are ready.

“We’re seeing a lot of attention being paid to 3D lately,” said Bernard Murphy, chief technology officer at Atrenta. “It’s getting a lot of air time with companies like ST and Qualcomm. Folks are trying to figure out how to combine more functionality into a chip. It’s a difference of using known pieces or trying to develop an overall optimized problem. A stacked die allows you to partition on the fly for a known device because you are not building those functions as part of a die.”

This is different from the system-in-package approach taken by memory makers, which have been churning out a rudimentary stacked die for several years in the form of flash or DRAM. That’s more of a system-in-package approach to put more memory into a single package.

The real work is under way inside R&D department at large companies and inside universities to develop chips that stack processing, logic and memory in various vertical layers, thereby reducing the amount of distance between the pieces and greatly simplifying timing and verification—currently the two biggest problems in developing SoCs. Initial versions most likely will contain two layers, but more layers will be added over time.

“The technology is not ready, and neither are the standards and the way all this technology gets used,” said Javier Delacruz, director of eSilicon’s packaging group. “But there is definitely a need for this. As we move down technology nodes and you can fit more on a chip, the cost per unit area is increasing. The best way to address that is to take the non-critical pieces off the chip. It’s a no-brainer. So you take out the memory and add an interface.”

Figure 1: 3D structure with through silicon vias. Source: MicroMagic
That also eases some of the power modeling issues for chips, he said. “Right now, everything is very high power because of the power supplies needed for all the parts of a chip and it’s thermally intensive. But with TSVs, you don’t need to drive a DDR at 1.8 volts.”

What also makes this approach attractive is the ability to mix and match lithographic geometries. A core for one function can be manufactured at a different process node than a core for a different function or a block of memory. In addition, the distances needed to reach various components can be shortened by stacking them rather than routing across a chip, where it can be affected by other traffic, Delacruz said.

What’s here, what’s missing
While this is considered a likely solution for building chips, it’s still largely a research project.

“3D TSV adoption is very application-driven,” said Rajiv Maheshwary, senior director for customer marketing at Synopsys. “In 2010 you will see MEMS, CMOS image sensors and homogenous memories in production. Heterogeneous system integration (logic + memory, logic + RF, logic + logic) will take some time—probably somewhere between 2011 and 2013—for several reasons. First, the supply chain is not ready. That includes the foundries, outsourced assembly and test and EDA tools. Second, the cost of building fine-grain TSVs in the 5 to 10 micron range needs to come down before design teams can move to 3D. And third, business issues exist such as who is best suited to make 3D devices and IP-related issues.”

Thermal issues also are a problem. Getting the heat out of a chip is hard enough in a single layer. In multiple layers, the heat generated through leakage can impact signal integrity or, in the worst case, destroy a chip. Maheshwary said that over time he expects to see three types of TSVs because of this—signal, power and thermal—each with a different pitch.

In addition, there need to be standards for design rules and via patterns, which need to be developed by the memory makers. Also needed are interfaces to improve communications across the chip. The long-term outlook includes separate clocks, separate power and logic to manage communications between the various components, said Geert Rosseel, vice president of technology at Arteris.

“The question from our standpoint is what happens in the middle,” he said. “You want a unified architecture but you also need to turn off certain parts of the chip. You need some way to manage all of that because on chip you may have 32-bit, 64-bit and 128-bit signals. The only way we know of doing that is by packetizing the communications over a unidirectional link with a network on chip structure.”

And finally, the existing tools need to be evolved to be able to do place and route and verification on stacked die. EDA companies say tools will have to be enhanced to focus on TSV modeling, which is largely thermo-mechanical analysis, design for test, physical design, and signoff, which includes parasitic extraction, timing/IR drop and thermal analysis.