Symptoms Of SoC Electromagnetic (EM) Crosstalk

By Anand Raman and Magdy Abadir

Have you ever had your silicon demonstrate unexpected behavior? Have you ever found unexplainable design failure or performance degradation? A number of issues could be the culprit – from overloaded signal nets, a noisy power grid, or increasing temperature – but one problem often overlooked is electromagnetic (EM) crosstalk.

Electromagnetic (EM) crosstalk is unwanted interference from one or more signals (aggressors) affecting another signal (victim) through energy coupling via electric (capacitive) and/or magnetic (inductive) field. Traditionally, crosstalk in SoC design has been viewed primarily as capacitive coupling driven, where the aggressor and the victim are present in close proximity, focusing on unwanted coupling between signal lines via parasitic capacitance.

The current design trends such as decreasing feature size, 10GHz+ clock / 10Gbps+ data line speeds, lower noise margin driven by low-power techniques, and tighter integration of high speed analog and RF blocks with digital logic means you can no longer ignore crosstalk through magnetic coupling. However, considering the impact of EM crosstalk on design analysis and sign-off is not simple.

Several reasons make EM crosstalk analysis challenging. For one, EM crosstalk induced problems do not neatly package themselves into a single signature failure. It often manifests as a degradation in some key performance criterion that varies from design to design. A typical “indicator” used to determine if the problem is beyond capacitive coupling is to see if RC extraction driven verification demonstrates the unexpected silicon behavior. This makes identifying EM crosstalk related issues challenging. And traditional digital design flows are not setup to find and analyze these inexplicable behaviors.

EM crosstalk impacts delay in unpredictable manner. Impact on timing for a particular critical path depends on the geometry of the path, its surroundings, and the nature of the switching activity in the path and its neighbors. Commonly used timing analysis tools and methodologies accounts for capacitive coupling from nearby nets but cannot accounts for magnetic coupling. Unlike capacitive coupling which reduces rapidly with distance, magnetic coupling can happen through large and complex loop path, making it is extremely difficult to identify potential contributing aggressor signals.

EM crosstalk can also negatively impact jitter. It is common to see significantly higher than expected clock jitter in silicon compared to the value predicted by RC-extraction based sign-off. Often times, the additional jitter is a result of unanticipated magnetic coupling from some combination of aggressors that were not considered.

Capacitive coupling and electromagnetic crosstalk can distort key signals in a design and create a variety of system level problems. The bit-error-rate in a transceiver system can be significantly degraded which could result in forcing the system to work at a lower speed. Higher than budgeted noise in analog/RF subsystems can be created due to electromagnetic coupling from other high-speed analog/RF signal, digital signals, or a combination of the two, leading to sub-optimal performance.

EM coupling from unknown analog/RF and/or digital signals can lead to “logic faults” – an inexplicable logic error caused by badly shaped digital signal. It can also lead to unexpected state changes in a state machine due to electromagnetically induced voltages in state machine control. An extreme case of this is a full chip reset due to EM coupling from a high-power RF block. These types of errors are very hard to detect and debug, especially if the EM coupling is intermittent and activity based.

It is very difficult to identify, isolate and mitigate inductive coupling since it can happen through relatively large non-obvious loops formed by structures outside the immediate neighborhood of a victim signal. To reproduce unexpected behavior, a staggeringly complex scope of physical structures need to be handled to create a complete EM model of signal nets of interest. All design elements can contribute to crosstalk including power/ground nets, bulk silicon substrate, package layers, bond/bump pads, seal rings, metal fills and de-coupling capacitance. Most of these structures have complex physical layouts that need to be properly meshed to extract resistance, capacitance, inductance, coupling capacitance and mutual inductance.

EM crosstalk is a real issue in SoC designs today. Workarounds such as adding excessive design margin by over buffering high speed lines, over shielding sensitive lines and adding lots of white spaces or using software to disable specific modes of functionality or effectively reducing throughput result in sub-optimal performance, missed market target and increased cost and risk.

Design teams need to adjust their mindset and methodology to start considering EM crosstalk issues early and often during the design cycle. They need to invest time and effort in identifying aggressor / victim combinations, creating tests for potential failure modes, extracting EM accurate models for these combinations, and running tests to identify and eliminate issues. No physical verification sign-off should be considered complete until critical aggressor / victim combinations are modeled and signed-off in parallel. And EDA providers will need to significantly increase the capacity of EM tools and create smart utilities that allow users to narrow potential aggressor / victim combination from vast sea of possibilities in their design.