Syntiant: Analog Deep Learning Chips

Intel Capital funds startup to put AI in low-power mobile devices.


Startup Syntiant Corp. is an Irvine, Calif. semiconductor company led by former top Broadcom engineers with experience in both innovative design and in producing chips designed to be produced in the billions, according to company CEO Kurt Busch.

The chip they’ll be building is an inference accelerator designed to run deep-learning processes 50x more efficiently than traditional stored-program architectures, according to the company. The processor uses custom analog neural networks to optimize performance at the transistor level, and saves power by keeping the weighting for matrix calculations in memory to reduce the data to be moved with every cycle. Its microwatt-level power requirements are low enough to allow OEMs to build inference into earbuds, smart sensors and other mobile devices, according to the company.

There are plenty of other ways to accelerate the inference portion of a deep-learning application, and the power cost is lower with FPGAs or custom ASICs than with traditional GPUs. But all of those approaches are power-hungry enough to keep mobile users close to charging stations.

“Most machine learning happens in the cloud and there’s no real solution for battery-powered devices at the edge,” Busch said. “We wanted to do that in a way that allowed the chip to be always on so there could be pervasive intelligence in edge device.”

In addition to Busch, Syntiant’s C-suite includes CTO Jeremy Holleman – an expert in analog design with experience at National Semiconductor and in DARPA projects, whose Ph.D. research focused on micro-power integrated circuits for neural interfaces. Management also includes Dave Garrett, vice president of hardware, whose whose Ph.D. and expertise focuses on digital signal processing, VLSI architecture and chip design flows,. Garrett is a former distinguished engineer and associate technical director in Broadcom’s office of the CTO. And Stephen Bailey, vice president of software engineering and chief architect at Syntiant, is a former chief technologist at Broadcom Switch. His Ph.D. CS is from the University of Chicago.

“The design we came up with is effectively a physical representation of a neural network using an analog circuit,” Busch said. “What the analog gets you is the ability to build an amplifier with a single transistor, rather than thousands with digital, and the ability to run most of your computation in memory, and keep the weights in memory so you don’t have to spend most of your time moving data around the processor, which is what accounts for most of the power consumption with existing chips.”

The chip is able to handle 500,000-parameter neural network designs and modify existing designs slightly to optimize the results so one chip with a single DNN design can handle most tasks, but the company can modify the design to accommodate advances in neural network design.

“We have some configurability that lets us build a basic case and then use a tool we created ourselves that takes TensorFlow and converts it to a VerilogA, which is how we can go from software to hardware in the chip,” he said. The result is modifiable to some extent, “so we can train the actual chip in manufacturing as a service for a customer who wants one of our chips to recognize two dozen specific words right out of the box.”

Those derivatives allow the company to tune performance of the chip to a certain extent, but changes that reflext major changes to the DNN model or parameters, “which you have to expect because we’re still in the early days and the state of the art is advancing,” would be done with a new version fo the chip every 12 to 18 months.

The chip is able to handle video or voice recognition and response, and is small enough to fit in earbuds, smart speakers, smartphones and other devices. The first commercial agreement is for a smart microphone with a neural decision processor, which Syntiant is building under agreement with Infineon Technologies.

Intel was the heavy hitter, but venture Capital firms Seraph Group, Danhua Capital and Embark Ventures also took part in Syntiant’s Series A funding, which was advertised as a way to allow OEMs to bring machine learning and AI to edge devices.

Syntiant hasn’t announced a ship date, but Busch said the first product will ship during the second half of this year.


Michael Mingliang Liu says:

Apologies in advance for inevitably oversimplifying – my guesstimate is that, at the core of these “AI-on-Edge” or “In-Memory-Computing” analog/mixed-signal IC companies’ offerings resides, IN ESSENCE, a CMOS Winner-Take-All (WTA) circuit whose output current is being controlled (or calibrated) by a PLL charge pump.

WTA circuit, neuromorphic processor, and artificial neural network (ANN) were once popular research topics in academia; from the 1980’s till 2000’s…

Love to hear/learn from others working on such circuits.

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