System Integration With Standards-Based Automation

Today’s semiconductor designs support a broad range of applications, from mobile and edge devices to AI accelerators and data center systems. To keep pace, design teams are shifting from monolithic systems-on-chip (SoCs) to increasingly complex multi-die and chiplet-based architectures. These heterogeneous systems often incorporate IP developed at different times, by different teams, or sourced from third parties. Managing this complexity requires a structured, standards-based approach that ensures consistent metadata representation across abstraction levels, design tools, and development teams. Without such a foundation, the benefits of scalable IP reuse and efficient integration are difficult to achieve, even when using proven IP blocks.

Most SoCs incorporate a mix of soft IP blocks and hard IP components sourced from multiple vendors, along with internally developed IPs. This proprietary customization is often what differentiates one product from another. While this approach accelerates development and leverages existing expertise, it also introduces complications. Each IP may come with its own naming conventions, documentation formats, and assumptions about integration, making the process of putting everything together slow and error-prone.

The task becomes even more challenging when assembling IP from different sources into a unified, top-level system. Design teams must manually interpret and reconcile inconsistent port definitions, parameter sets, memory maps, and bus interfaces. Critical metadata is often buried in spreadsheets or plain-text documentation, leaving room for misinterpretation and integration mistakes. As systems scale, the lack of a consistent structure and automation-friendly format becomes a bottleneck for both verification and reuse.

A structured foundation for scalable IP integration

A more effective solution begins with a standard, machine-readable way to describe IP components that supports both individual block integration and system-level assembly. This description should include all relevant interface information, from bus protocols to register maps, and it must be flexible enough to support a range of abstraction levels. This foundation enables scalable automation and reduces integration risk.

To address these challenges, the industry has adopted IP-XACT, an XML schema defined by IEEE 1685. It enables consistent, tool-agnostic metadata descriptions, including ports, parameters, bus interfaces, memory maps, and filesets. These standardized representations support both individual IP blocks and hierarchical assemblies such as subsystems, chiplets, SoCs, and multi-die systems. By capturing this information in a structured, reusable format, IP-XACT improves interoperability between IP providers, design teams, and EDA tools while enabling early issue detection and reliable integration.

Standards-based automation for IP description

Building on the foundation provided by the IP-XACT standard, Magillem Packaging extends the Arteris system IP platform by automating the extraction and formatting of component descriptions compliant with the 2022 specification. It enables design teams and IP providers to capture and package IP in a way that aligns logical, register, and interface-level views with a single XML-based representation. Built-in support for hierarchical design structures, protocol-aware interfaces, and multi-view packaging helps maintain alignment across development teams while ensuring compliance with IP-XACT semantics and schema rules.

Fig. 1: Magillem Packaging facilitates IP reuse and design integration. (Source: Arteris)

Magillem Packaging incorporates a dedicated suite of checkers to validate the structure and content of descriptions generated according to the standard. This ensures data consistency across teams and facilitates the reuse of IP across multiple projects. The tool supports legacy IP-XACT 2009 and 2014 formats and includes converters to the latest 2022 schema. This allows teams to preserve prior work while adopting the latest capabilities. These enhancements include improved SystemVerilog support, better handling of connectivity constructs, and new features for managing memory objects, parameterized registers, and mixed abstraction views.

The tool streamlines SoC assembly by automating port-to-interface mapping, enabling protocol-aware connectivity, and reducing manual inter-IP configuration. It supports fileset elaboration and multi-view packaging, allowing teams to maintain distinct setups for simulation, synthesis, emulation, and fault injection. These capabilities establish a consistent abstraction layer that ensures design correctness, facilitates early issue detection, and supports reliable propagation of memory maps throughout the system. Check out the Accelerating IP Reuse tech talk video with Ed Sperling to learn more.

A unified flow for integration and reuse

Beyond IP description, integration automation continues with Magillem Connectivity, which assembles SoCs and chiplets by managing interconnects, hierarchies, configurations, and top-level netlists. It enables structured data capture for interfaces and parameters and generates the collateral required for simulation, synthesis, and implementation.

Completing the integration flow, Magillem Registers addresses the hardware/software boundary by automating register modeling and ensuring system-wide memory map consistency. It provides a single source of truth across firmware and hardware teams, generating C headers, UVM models, and documentation directly from the register specification.

Fig. 2: Magillem SoC integration automation tools derisk designs and accelerate TTM. (Source: Arteris)

Together, these Arteris tools establish a structured approach to SoC design, with distinct roles across the integration flow. Magillem Packaging defines the component; Magillem Connectivity assembles it into a system; and Magillem Registers ensures alignment at the hardware/software boundary. Each is available as a standalone tool, but when used together, they form a cohesive automation flow from IP definition to final SoC or multi-die integration. For more information, go to www.arteris.com.