tag: 10nm

Pathfinding Beyond 10nm
By Paula Doe - 10 Aug, 2015 - Comments: 0

After higher aspect-ratio finFETs and higher mobility SiGe and III-V materials, the industry will move to lateral nanowires and then to vertical nanowire transistors, and to new tunnel junction FETs or spin wave architectures ─ or to various combinations of these technologies for different applications, reported An Steegan, Imec senior vice president of process technology, during SEMICON West... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 10 Aug, 2015 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about acquisitions, software and EDA. What follows are excerpts of that interview, which was conducted in front of a live audience at DAC. SE: A lot of Synopsys' investments are moving in a new direction, namely software. Why is that becoming so important to your company? De Geus: It's not a dif... » read more

Which Process, Material, IP?
By Ed Sperling - 30 Jul, 2015 - Comments: 1

For years chipmakers have been demanding more choices. They've finally gotten what they wished for—so many possibilities, in fact, that engineering teams of all types are having trouble wading through them. And to make matters worse, some choices now come with unexpected and often unwanted caveats. At the most advanced nodes it's a given that being able to shrink features and double patter... » read more

Rethinking Manufacturing Models
By Ed Sperling - 23 Jul, 2015 - Comments: 0

The perennial uncertainty surrounding EUV lithography and complications stemming from the most advanced nodes are creating a domino effect across the semiconductor industry. Rather than stalling the market, though, which is what happened with the transition to 20nm, vendors now are accelerating their product rollouts and adjusting business plans to capitalize on those delays. That includes m... » read more

Inside Samsung’s Foundry Biz
By Mark LaPedus - 23 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about the foundry business, process technology, design and other topics with Hong Hao, senior vice president of the foundry business at [getentity id="22865" e_name="Samsung Semiconductor"]; and Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. What follows are excerpts of that discussion. SE: The foundry business has alway... » read more

Tech Talk: Wafer Plane Analysis
By Ed Sperling - 23 Jul, 2015 - Comments: 0

Leo Pang, executive vice president at D2S, talks about the problems of patterning at 40nm and below and how to deal with them more effectively using existing equipment. [youtube vid=FbRyhw2q3fE] » read more

What Will 7nm And 5nm Look Like?
By Mark LaPedus - 23 Jul, 2015 - Comments: 0

Citing an assortment of undisclosed manufacturing issues, Intel in July pushed out the introduction of its 10nm chip and process technology to the second half of 2017. This is roughly six or more months later than expected. With the delay at 10nm, [getentity id="22846" e_name="Intel"] also pushed out its process cadence from 2 to 2.5 years. Other foundries, meanwhile, are struggling to keep ... » read more

Tech Talk: 22nm FD-SOI
By Ed Sperling - 13 Jul, 2015 - Comments: 0

Subramani Kengeri, vice president of global design solutions at GlobalFoundries, discusses the evolution of 22nm FD-SOI and its advantages, including single patterning in the middle end of line, 0.4 volt operating voltage, and how it compares to finFETs in terms of performance. [youtube vid=5fa1AcIGcUw] » read more

Moore’s Law Reset?
By Ed Sperling - 13 Jul, 2015 - Comments: 0

GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore's Law technologically without altering the economic equation—at least for the next couple of process nodes. Subramani Kengeri, vice president of global design solutions at [getentity id="22819" comment="GlobalFoundries"], said 22nm FD-SOI will provide the same 30% improvement in PPA that has been c... » read more

Here Comes 7nm
By Ed Sperling - 09 Jul, 2015 - Comments: 0

A consortium of companies involving IBM, GlobalFoundries and Samsung has rolled out the first 7nm test chip using silicon germanium as a substrate, using EUV to pattern multiple layers. While this doesn't mean the cost equation is even close to being solved, or that more than a handful of companies will push forward to that node anytime soon using SiGe as the substrate material, it does cre... » read more

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