tag: 14nm

Designing For Energy Efficiency
By Ed Sperling - 06 Nov, 2014 - Comments: 0

Swiss watchmakers have nothing to worry about for the moment. As top-name companies crowd into the wearable market with full-featured watches, limits on battery life and frequent charges undoubtedly will limit their popularity. Smart watches look cool or clunky, depending upon your perspective, but none of them lasts long enough between charges to be a serious market contender. That's certai... » read more

Design Rules Explode At New Nodes
By Ed Sperling - 03 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Why Is My Device Better Than Yours?
By Ed Sperling - 23 Oct, 2014 - Comments: 0

Differentiation is becoming a big problem in the semiconductor industry with far-reaching implications that extend well beyond just chips. The debate over the future of [getkc id="74" comment="Moore's Law"] is well known, but it's just one element in a growing list that will make it much harder for chip companies, IP vendors and even software developers to stand out from the pack. And withou... » read more

IBM Unloads Chip Biz To GF
By The SE Staff - 20 Oct, 2014 - Comments: 0

By Ed Sperling & Mark LaPedus After months of on-again, off-again negotiations, [getentity id="22306" comment="IBM"] agreed to hand over its Microelectronics unit to [getentity id="22819" comment="GlobalFoundries"] for $1.5 billion—meaning IBM will actually pay GlobalFoundries that amount to get rid of what has become an albatross for Big Blue. To really sweeten the deal, GlobalFoundr... » read more

Design Rules Explode At New Nodes
By Ed Sperling - 16 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

The Impact Of 14nm Photomask Uncertainties On Computational Lithography Solutions
By Mentor, a Siemens Business - 16 Oct, 2014 - Comments: 0

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, in turn, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned... » read more

The Real Numbers: Redefining NRE
By Ed Sperling - 26 Sep, 2014 - Comments: 0

Developing ICs at the most advanced nodes is getting more expensive, but exactly how much more expensive is the subject of debate across the semiconductor industry. There are a number of reasons for this discrepancy. Among them: As design flows shift from serial to parallel, it's hard to determine which groups within companies should be saddled with different portions of the bill. The re... » read more

Which Comes First?
By Ed Sperling - 25 Sep, 2014 - Comments: 0

Methodologies in IC design typically follow tools. The tools enable the methodologies, and chipmakers' businesses are built around both of them. That has been the rock-solid foundation for the design and production of chips since well before the impenetrable 1-micron wall. But that approach is falling apart at 28nm, and it will continue to crumble at 16/14nm and 10nm. It simply isn't fast en... » read more

Challenges Increase for IP At Advanced Nodes
By Ann Mutschler - 25 Sep, 2014 - Comments: 1

At advanced process nodes such as 16/14/10nm, designing [getkc id="43" comment="IP"] is a much tougher nut to crack due to complexity and other considerations, not to mention then trying to migrate and/or re-use that IP. Still, engineering teams are looking for leverage wherever they can find it in their designs amid the technical challenges to overcome. Tomasz Wojcicki, vice president of c... » read more

Quantifying IP Entitlement For 14/16nm Technologies
By eSilicon - 24 Sep, 2014 - Comments: 0

The scaling benefits of [getkc id="74" comment="Moore"s Law"] are being seriously tested at 28nm. It is no longer a given that the cost per gate will go down at leading edge process nodes below 28nm, e.g., 20nm though 14nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex [getkc id="81" comment="SoC"] (So... » read more

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