Stacks And Stacks

By Ed Sperling - 28 Jul, 2011 - Comments: 0

Talking about stacked die is sort of like describing Africa as a country. First of all, it’s wrong—despite some politicians’ statements to the contrary. And second, lumping everything together under a single heading probably adds more confusion than clarity. There are several ways to approach this semantics problem. One is by function. Memory on memory, memory on logic, and logic on l... » read more

Experts At The Table: Multi-Foundry Strategies

By Ed Sperling - 26 Jul, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president ... » read more

The Future Of ASICS In 3D

By Javier DeLaCruz - 26 May, 2011 - Comments: 0

By Javier DeLaCruz 3D technology is generating a lot of interest as a way to reduce NRE costs and speed time to market. This is still a nascent approach, so people are looking for a single standard in through-silicon vias (TSVs), primarily to reduce infrastructure costs. Unfortunately, I do not think this will be possible. There are at least two fundamentally different applications for 3D t... » read more

Behind The Analog Frenzy

By Ed Sperling - 08 Apr, 2011 - Comments: 0

Analog is suddenly very hot again, and much of it appears to be due to the promise of 2.5D and 3D stacking. Texas Instruments pulled out its checkbook to pay $6.5 billion for National Semiconductor, and Microsemi has offered $28 million for AML Communications, which makes low-noise and high-power microwave amplifiers. So what’s behind these move? In TI’s case, there appears to be a re... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: 2.5D stacking

Stacks And Stacks

Experts At The Table: Multi-Foundry Strategies

The Future Of ASICS In 3D

Behind The Analog Frenzy