tag: 20nm

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 20 Jun, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: What’s changing in the ecosystem and ho... » read more

Tech Talk: FinFETs, FD-SOI And The Future Of SoC Design
By Ed Sperling - 04 Jun, 2013 - Comments: 0

Mary Ann White, marketing manager for Synopsys' Galaxy Implementation Platform, talks with Low-Power/High-Performance Engineering about new opportunities to reduce power and improve performance, and where the pain points will be. [youtube vid=kuJdcHIRxfU] » read more

Bigger Wafers, Bigger Risk
By Ed Sperling - 16 May, 2013 - Comments: 0

At 22/20/16/14nm the semiconductor industry is experiencing a rather new twist on Moore’s Law. Smaller, as in smaller feature sizes, is no longer assumed to be cheaper—or at least not for everyone. In fact, the cost per transistor for the first time in more than half a century could rise in some cases. Whether this outlook improves as the semiconductor industry gains more experience wit... » read more

Executive Briefing: Andrew Yang
By Ed Sperling - 09 May, 2013 - Comments: 0

By Ed Sperling Andrew Yang, president of ANSYS subsidiary Apache Design, sat down with Low-Power/High-Performance Engineering to talk about why power is becoming so important and where the future challenges lie. What follows are excerpts of that conversation. LPHP: What’s the most important issue these days for chipmakers? Yang: According to the feedback we’ve gotten from our customer... » read more

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 26 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts o... » read more

Design Topology Requires Physical Data
By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 19 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts o... » read more

The Evolving Interconnect
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

Nanoscale Wiring
By Kathryn Ta - 21 Mar, 2013 - Comments: 0

By Kathryn Ta The TEM image (below) taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in cross section. These tiny structures – about 1/5000th of the diameter of an average human hair – are similar to the interconnects used to wire the billions of transistors in next-generation microchips. You can see that each trench is partially filled with coppe... » read more

What’s In A Name?
By Subi Kengeri - 20 Mar, 2013 - Comments: 0

By Subi Kengeri Consumers continue to demand smaller, faster and more energy-efficient electronic devices, driving the semiconductor industry to accelerate development of commercially viable chips on more advanced nodes. However, these new nodes don’t just appear by magic. It takes a great deal of careful planning to develop and deliver a process technology platform that offers competitivene... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy