tag: 28nm

Trouble Spots And Optimism For 2015
By Ed Sperling - 18 Dec, 2014 - Comments: 0

Most top executives in the semiconductor industry are bullish about 2015 and even beyond, particularly as the [getkc id="76" comment="Internet of Things"] begins to drive new markets and market mash-ups, and as more semiconductors find their way into markets such as automotive, health-care and manufacturing. But it's not an entirely rosy picture, and top executives point to potential trouble sp... » read more

What’s The Other Guy Doing?
By Ed Sperling - 11 Dec, 2014 - Comments: 0

Competition is generally a good thing. It improves service, promotes innovation, forces efficiencies and price cuts where necessary, and it ratchets up the pressure to bring products and services to market faster. Those who can't keep up usually lose market share, and eventually the business sector consolidates until something comes along to disrupt it. That cycle has been repeated in every ... » read more

Signal And Power Integrity Cross Paths
By Ed Sperling - 05 Dec, 2014 - Comments: 2

Signal integrity and power integrity historically have been relatively independent issues, and engineers with expertise in one area generally operate independently of the other. But as more power domains are added to conserve energy and allow more features, as voltages are reduced to save battery life, and as dynamic power becomes more of a concern at advanced nodes, these worlds are suddenly m... » read more

Design Rules Explode At New Nodes
By Ed Sperling - 17 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Designing For Energy Efficiency
By Ed Sperling - 06 Nov, 2014 - Comments: 0

Swiss watchmakers have nothing to worry about for the moment. As top-name companies crowd into the wearable market with full-featured watches, limits on battery life and frequent charges undoubtedly will limit their popularity. Smart watches look cool or clunky, depending upon your perspective, but none of them lasts long enough between charges to be a serious market contender. That's certai... » read more

Design Rules Explode At New Nodes
By Ed Sperling - 03 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Design Rules Explode At New Nodes
By Ed Sperling - 16 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Challenges Increase for IP At Advanced Nodes
By Ann Mutschler - 25 Sep, 2014 - Comments: 1

At advanced process nodes such as 16/14/10nm, designing [getkc id="43" comment="IP"] is a much tougher nut to crack due to complexity and other considerations, not to mention then trying to migrate and/or re-use that IP. Still, engineering teams are looking for leverage wherever they can find it in their designs amid the technical challenges to overcome. Tomasz Wojcicki, vice president of c... » read more

Why Investments At Advanced Nodes Matter
By Ed Sperling - 18 Sep, 2014 - Comments: 0

Despite all the talk about rising costs of development, uncertainties about lithography and talk about the death of Moore’s Law, a record number of companies are developing chips at 16nm/14nm. That may sound surprising, but asking why that’s happening is probably the wrong question. The really critical question is what they’re going to do with those chips. What’s become quite evident... » read more

The Route To Faster Physical Verification And Better Designs
By Jean-Marie Brunet - 18 Sep, 2014 - Comments: 0

By Nancy Nguyen & Jean-Marie Brunet As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to converge, power reduction for both IR and leakage becomes a big issue, and most importantly, how do we meet all of the ever-growing and more complex signoff d... » read more

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