tag: 3D-IC

All Together Now!
By Karen Savala - 30 Jun, 2014 - Comments: 0

Consolidation is changing the face of our industry. It is tempting to think that a narrower more consolidated industry is easier to navigate and might require less facilitated coordination and collaboration. However, it turns out the reverse is true. With fewer, but much bigger companies, the bets become exponentially bigger.  At the same time technical challenges — such as advanced tra... » read more

Test Challenges Grow
By Mark LaPedus - 09 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: In our l... » read more

Executive Insight: Simon Segars
By Ed Sperling - 03 Jun, 2014 - Comments: 0

SE: What concerns you most? Segars: In the context of design and where chip design is going, ARM is a long-term business. We’re doing stuff now that is going to ship in five years’ time. Obviously, for everyone in this space, Moore’s Law has been a fantastic thing. It’s enabled us to achieve really fantastic scaling of transistors, and everyone knows that is getting harder and harder... » read more

Shootout At 28nm
By Ed Sperling - 15 May, 2014 - Comments: 0

By Ed Sperling & Mark LaPedus Samsung, Soitec and STMicroelectronics are joining forces on 28nm FD-SOI, creating a showdown with TSMC and others over the best single-patterned processes and materials and raising questions about how quickly companies need to move to the finFET technology generation. The multi-source manufacturing collaboration agreement for fully depleted silicon-on-insulato... » read more

Beyond Moore’s Law
By Michael Watts - 15 May, 2014 - Comments: 0

What do you make of all the different reports coming out of Advanced Lithography 2014 — the end of Moore's Law, continued problems with EUV, directed self-assembly assembly makes progress? An equipment insider, whose judgment I value, came back from the meeting and concluded, "We will see the end of Moore’s Law shrinks in 2020. After that, no one knows!” There is no way a $300B+ business ... » read more

IP To Meet 2.5D Requirements
By Ann Mutschler - 08 May, 2014 - Comments: 1

The semiconductor industry is still in the early stages of evolution in the realm of 2.5D, but when these devices do come out, the IP used on them will have to be brand new, according to Javier DeLaCruz, senior director of engineering at eSilicon. “The IP causes the biggest risk that you’re going to have in this implementation,” he said. “Everything else in here for making those ASIC... » read more

Powerful Memories
By Brian Bailey - 07 May, 2014 - Comments: 1

Memory consumes more of the surface area of a die than any other component. So what changes have happened over the past few years to reduce the power consumption of memories, and where are the big opportunities for saving power? Let's take a closer look. A Growing Concern One of the key drivers for SoCs is the desire to reduce product costs, reduce form factors, reduce power, increase perfo... » read more

Executive Insight: CH Wu
By Ed Sperling - 21 Apr, 2014 - Comments: 0

Semiconductor Engineering sat down with CH Wu, president and CEO of Advantest Taiwan, to talk about business, politics, and his philosophy on what really motivates people. What follows are excerpts of that conversation. SE: Tell us a little about who you are and your background. Wu: I graduated from college with a degree in electrical engineering and started at Philips Electric, then moved ... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

Time To Revisit 2.5D And 3D
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

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