Different Approaches Emerge For Stacking Die

First of two parts: While full logic-on-logic 3D ICs are still in the experimental stage, other approaches are beginning to take shape.

popularity

The concept of stacking die to shorten wires, improve performance, and reduce the amount of energy required to drive signals has been in research for at least the past dozen years at both IBM and Intel. And depending upon whom you ask, it could be another 2 to 10 years before it becomes a mainstream packaging approach—if it happens at all.

At least part of the confusion stems from how you define a 3D ICs architecture. The classic definition that has emerged is logic on logic, connected with through-silicon vias and designed from the ground up. But there are other iterations of this idea, ranging from package-on-package (PoP), homogeneous memory stacks on logic, and hybrid chips that combine some elements of 2.5D with 3D memory and almost-3D memory. There are even some new approaches being presented, including wireless connectivity between very thin die, and wafer-level packaging rather than die-on-die packaging.

The picture emerging from all of these different approaches is that companies are experimenting with many different ideas as it becomes more difficult and expensive to shrink features beyond 20nm, and particularly at 10nm as the power and performance benefits of those shrinks become harder to justify. FinFETs certainly help reduce leakage current, for example, but moving from a 16/14nm finFET to a 10nm finFET doesn’t provide the same benefits in energy reduction as moving from a 20nm planar transistor to a 16/14nm finFET.

2.5D or 3D?
Conventional wisdom over the last five years has been that 2.5D IC packaging—chips arranged in a planar fashion around an interposer—would become the steppingstone to 3D. The idea was that interposers gradually would be replaced by through-silicon vias as chips are thinned out and bonded together. But there is a fair amount of debate these days about the accuracy of that prediction.

“Both of these technologies—2.5D and 3D—will exist together for many years to come,” said Dan Lueng, director of packaging and assembly at Open-Silicon, adding that business reasons will continue to sustain the 2.5D packaging approach. “We can see a parallel between the multi-chip module vs. SiP transition, which has been occurring for many decades now. Early work has shown improved system performance and much smaller physical size when the packages are removed, and only die-to-die communication remains. However, the stumbling block has always been trying to determine a business model by which SiP package will work, addressing the liability, testability and compounding yield questions that determine the product’s success in the marketplace.”

Not everyone is convinced full 3D ICs will see much mainstream use, in the short term and maybe not even in the long term.

“In the mainstream sense, there is a perception that the cost of true 3D is not economically viable,” said Steve Schulz, president and CEO of Si2. “There is a question about whether all of the technology issues are solved. And there are questions surrounding the business model regarding who does what and who assures what.”

Schulz noted that stacked die remain one of the more attractive ways to continue functional integration, but he said that doesn’t necessarily mean a 3D-IC using TSVs. “There are a lot of technologies being considered. If you look at communication bandwidth, photonics offers three orders of magnitude improvement, which will drive a faster rate of commercialization.”

The silence is deafening
What’s becoming clear is that the initial exuberance about this approach underestimated the challenges—both business and technical—which is why the first wave of 3D ICs will be stacked memory on logic, through the Hybrid Memory Cube (HMC) approach, and high-bandwidth memory, which is more of an evolutionary extension of DRAM. Intel, one of the original backers of the HMC architecture, plans to use the technology with its high-performance Knights Corner “many integrated core” processor.

What’s less obvious is whether this approach will ever be worth extending beyond memory. “We are not seeing much heterogeneous logic on logic,” said Michael White, product marketing director for Mentor Graphics’ Calibre physical verification products. “There is an effort with the Institute for Technology Research in Nanoelectronics (IRT) and the French government, which is die on die, but that’s largely research-oriented.”

That is consistent with the buzz about 3D ICs in general. While 2.5D is gaining momentum, development of full 3D ICs seems to have gone dark.

“The fact that it’s so quiet either means the industry is busy working on it, or something has stalled,” said Kurt Shuler, vice president of marketing at Arteris. “We definitely are getting more questions these days about how to scale our technology with TSVs from all over the place. But that’s also followed by, ‘What are you hearing and seeing?’ And the reality is that if you add TSVs, you probably have to redesign the hardware. If you own all the pieces, like a Micron or SK Hynix, it may make sense. For others, that’s not clear yet.”

Redefining 3D IC
What exactly constitutes a 3D IC also is in flux. The Hybrid Memory Cube, for example, uses homogeneous memory chips connected to a base logic layer, rather than stacks of heterogeneous chips put together using different process technologies, which was the original concept behind 3D ICs. But as the challenges of building these chips increases, the vision of how to build a 3D IC also is changing—sometimes to hybrids of 2.5D and 3D.

“If you talk to the TSV people, they think their approach will be cheaper in the end,” said Drew Wingard, chief technology officer at Sonics. “But right now the only chips that need TSVs are homogeneous memory chips. Combining mixed signal and memory is a much harder problem. Even with HMC, the logic die doesn’t need a TSV. And with package-on-package, it may look more expensive than full 3D because you have bond wires around the edges, but it solves the known good die problem because you can test the chips individually. You can’t do that in a full 3D stack. Testing is the hardest part.”

It’s not that some sort of stacking approach isn’t necessary. The time-to-market constraints of the Internet of Things and the flexibility that stacked die can provide are big steps forward in semiconductor design. But how to get there most effectively is a work in progress.

“My take is that 3D is going to be limited to the handheld market because there is a fundamental heat dissipation issue,” said Javier DeLaCruz, senior director of engineering at eSilicon. “If you stack the heat sources on top of each other, it is hard to manage the heat, so you need to generate little heat to accomplish this. The only guys with applications that are this low power are in the handset market. Unfortunately, the industry started with 3D due to success with the MEMS market, which needed it for basic functionality and a cost reduction. For cell phone application processors, it will cost more than the existing solution. Some mobile handset chipmakers may have been overzealous in pushing the memory guys into supplying Wide I/O memory in a market unable to bear the additional cost.”

DeLaCruz said the cost curve needs volume, and that volume will have to come from 2.5D. “3D applications need to accept that they will need to pay a premium for the area saving—height, as well—and they are unwilling to accept it. But 2.5D has some serious legs on it.”

There are other definitions of 3D creeping in, though. Kevin Rinebold, senior product marketing manager for packaging line tools at Cadence, said the push toward thinner devices such as phones and tablets will continue to change packaging schemes.

“We’re already seeing package on package configurations where there is a flip chip on the bottom and memory on the top package,” said Rinebold. “Is this 3D? It’s wire-bonded and the package has substrate laminates. But in the last 9 to 12 months we’ve also seen a push toward even thinner devices using wafer-based packaging. This is one of several pathways to full 3D integration, and it’s a viable alternative to the traditional idea of stacking.”

He’s not alone in this view. Si2’s Schulz believes that “system on chip” likely will migrate to “system on stack,” primarily driven by the needs of the automotive and Internet of Things markets.

But there also are cross-currents in packaging, new technology approaches emerging, and gaps in the tools. This will be dealt with in the second part of this series.



  • Dev Gupta

    Ed :

    consider including in the Part II of your article issues in extending the performance of the PoP package to higher bandwidth etc. or making them thinner like 3d stacks ( e,g. Wide I/O ) w/ TSVs. For elegant solutions using current technologies to get performance like 3d stacks BUT w/o having to introduce TSVs into live chips, look up the technical literature for Super PoP and Magic Chip by APSTL.