Stacked Die Changes

By Ed Sperling - 27 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of tha... » read more

To 7nm And Beyond

By Ed Sperling - 21 Jul, 2016 - Comments: 4

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], and Thomas Caulfield, senior vice president and general manager of Fab 8, sat down with Semiconductor Engineering to discuss future directions in technology, including the next rev of FD-SOI, the future of Moore’s Law, and how some very public challenges will likely unfold. SE: What do you see as the... » read more

Building Faster Chips

By Ed Sperling - 21 Jul, 2016 - Comments: 5

By Ed Sperling and Jeff Dorsch An explosion in IoT sensor data, the onset of deep learning and AI, and the commercial rollout of augmented and virtual reality are driving a renewed interest in performance as the key metric for semiconductor design. Throughout the past decade in which mobility/smartphone dominated chip design, power replaced performance as the top driver. Processors ha... » read more

Stacking Logic On Logic

By Katherine Derbyshire - 21 Jul, 2016 - Comments: 0

Advanced packaging can be an alphabet soup of possible approaches, from heterogenous integration of multiple die types into a single package, to three-dimensional stacking of multiple dies on top of each other. Three-dimensional chip stacking is most commonly seen in memory devices. Applied to logic, though, there are at least two different ways for integration to proceed. Completely process... » read more

Interconnect Challenges Rising

By Mark LaPedus - 27 Jun, 2016 - Comments: 1

Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

Advanced Packaging Options, Issues

By Ed Sperling - 23 Jun, 2016 - Comments: 0

Systems in package are heading for the mass market in applications that demand better performance and lower power. As they do, new options for cutting costs are being developed to broaden the appeal of this approach as an alternative to shrinking features. Cost has been one of the big deterrents for widespread adoption of [getkc id="82" kc_name="2.5D"]. Initially, the almost universal compla... » read more

Performance First

By Ed Sperling - 16 Jun, 2016 - Comments: 0

Crank up the clock speed. It takes a lot more performance to run virtual reality smoothly, or to process data in the cloud, or to stream a high-definition video from a drone. And none of that compares to the amount of performance required to kill an array of disturbingly realistic zombies on a mobile device in conjunction with other players scattered around the globe. After several years of ... » read more

The Evolving Thermal Landscape

By Ann Mutschler - 16 May, 2016 - Comments: 0

Managing heat in chips is becoming a precision balancing act at advanced nodes and with advanced packaging. While it's important to ensure that temperatures don't rise high enough to cause reliability problems, adding too much circuitry to control heat can reduce performance and lower energy efficiency. The most common approach to dealing with these issues is thermal simulation, which requir... » read more

2.5D Becomes A Reality

By Ed Sperling - 11 May, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

Why This Roadmap Matters

By Ed Sperling - 05 May, 2016 - Comments: 0

The semiconductor industry is now officially looking beyond PCs and servers, establishing metrics and guidance for existing and developing market segments rather than just focusing on how to get to the next process nodes. The IEEE's International Roadmap for Devices and Systems marks a fundamental shift in the industry. The uncertainty that has ensued ever since the introduction of 3D transi... » read more

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tag: 3D-IC

Stacked Die Changes

To 7nm And Beyond

Building Faster Chips

Stacking Logic On Logic

Interconnect Challenges Rising

Advanced Packaging Options, Issues

Performance First

The Evolving Thermal Landscape

2.5D Becomes A Reality

Why This Roadmap Matters

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