Advanced Packaging Requires Better Yield

Why the discussion about known good die is suddenly so important again, and how to achieve it.


Whether Moore’s Laws truly ends, or whether the semiconductor industry reaches into the Angstrom world after 3nm—the semiconductor industry dislikes fractions—advanced packaging increasingly will dominate semiconductor designs.

Apple already is on board with its iPhone 7, using TSMC’s fan-out approach. And all of the major foundries and OSATs are lining up with a long list of capabilities and options. Whether a chip is packaged by ASE, STATS ChipPAC or Amkor, or whether that work is done by GlobalFoundries, Samsung or UMC, the next big bet is on finding the best implementations of fan-outs, 2.5D, and monolithic 3D-ICs.

The primary driver for all of this work, as with most things related to semiconductors, is economics. It’s too expensive at every level of the semiconductor ecosystem to continue pushing chip development at the most advanced nodes. Companies developing chips at 5nm or 3nm will likely be developing them for very specific purposes, or they will be developing platform processors that can be sold for advanced packaging, possibly in the form of extremely uniform chiplets.

This isn’t the end of the road for anyone. As Daniel Green, program manager for DARPA’s Microsystems Technology Office, pointed out, this isn’t “More than Moore.” It’s “More of Moore.”

In fact, the roadmap continues to get more complex. What changes is that the complexity is now split apart into discrete components, essentially a divide-and-conquer approach to manufacturing. The idea is that in smaller pieces, this complexity becomes more manageable.

There is some basis to that logic. Design teams have been using that approach for the past decade with great success, and despite the need for some overall system-level modeling, simulation and verification, truly understanding the individual pieces can make the whole device better.

This isn’t business as usual on the manufacturing side, though. The overall direction of Moore’s Law has been to squeeze everything onto one chip, and in the case of IP those blocks have largely been soft, synthesizable IP. Combing hard IP “chiplets” or “dielets” is more of an assembly and physical integration process, and it changes everything from how and when they are connected together to how this all gets tested.

Test is an important element in this. It’s one of the last big challenges with advanced packaging. It requires everything from a consistent methodology to more standardized ways of connecting everything together. Right now, there is debate about when to test, what to test, and how to do it, because the test process itself can ruin a known good die, dielet, chiplet, IP block, or whatever the correct terminology ultimately will be. But getting testing right also requires the entire industry to agree on the best packaging approaches rather than trying out all of them.

There is work underway to add more consistency. Standards groups are working on every facet of packaging, with a roadmap expected out by the end of March. Once that is in place, presumably there will be a set of best practices for putting together different technologies, which in turn will allow economies of scale to kick in so the entire semiconductor industry can move forward with much firmer footing. And for the first time, there should be some confidence that when a known good die is developed for inclusion in a package, that it will emerge out the other side as a known good piece of a fully functional device.

Related Stories
Making 2.5D, Fan-Outs Cheaper
Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.
Packaging Wars Begin
OSATs and foundries begin to ramp offerings and investments in preparation for mainstream multi-chip architectures.
Advanced Packaging Options, Issues
New fan-out technology under development; 2.5D trouble spots come into focus.
Inside Advanced Packaging
One-on-one with Amkor’s R&D chief about why and where 2.5D and fan-outs are gaining traction, and what’s coming next.
Keeping The Whole Package Cool
Thermal issues become more complex in advanced packaging.


Dev Gupta says:

Silicon Valley is NO LONGER qualified to talk about Manufacturing or the Sciences behind it that are needed for Yield Improvement or making rational technology / partitioning choices. Most new Transistors are now poineered in OR, for the last quarter century most Advanced Packaging in use today have been developed in AZ or NY. The Fabless Wonders ( FW ) of Silicon Valley use these very same technologies originally developed at US IDMs and then recycled by overseas Foundries and OSATs. As these FW have no internal R&D on Manufacturing Sciences to speak of, they remain totally dependent on their overseas enablers for new Manuf. technologies. Which is why we find them forced to use expensive 2.5 d Dual Damascene Si Interposers for GPUs while IDMs with deep knowledge base are able to provide processors for Servers and even Super Computers using older and cheaper Adv. Packaging technologies, yet deliver similar GFlops, Bandwidth and Power Efficiencies at a lower cost. Publications in silicon Valley may opine / bloviate about Manufacturing, Yield or KGD but invariably these turn into vague discussions on Design which is all the now emasculated Valley is left with.

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