tag: 3DIC

A Novel Tier Partitioning Method in 3DIC Placement Optimizing PPA
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation" was published by researchers at Seoul National University and Ulsan National Institute of Science and Technology. Abstract "3D ICs are renowned for their potential to enable high-performance and low-power designs by utilizing denser and shorter inter-tier connections. In the physical design f... » read more

Thermal-Aware DSE Framework for 3DICs, With Advanced Cooling Models
By Technical Paper Link - 11 Mar, 2025 - Comments: 0

A new technical paper titled "Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs" was published by researchers at University of Michigan, Shanghai Jiao Tong University and University of Virginia. Abstract "The rapid advancement of three-dimensional integrated circuits (3DICs) has heightened the need for early-phase design spa... » read more

3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation and Carnegie Mellon University. Abstract "This article presents Omni 3D—a 3-D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D interleaves metal lay... » read more

Pre-Silicon Verification Of Die-to-Die IP With Novel ESD Protection
By Synopsys - 26 Feb, 2025 - Comments: 0

All major foundries have adopted the programmable electrical rule checker (PERC) as the pre-silicon electrostatic discharge (ESD) signoff tool for IP and chip designs. This concept of rule checking works fine for most IP types, but for die-to-die IP, used in 3DIC designs, the PERC approach may not be appropriate. Die-to-die interface IP includes extremely large numbers of I/Os, trending towards... » read more

Thermal Analysis Of 3D Stacking And BEOL Technologies With Functional Partitioning Of Many-Core RISC-V SoC
By Cadence - 26 Feb, 2025 - Comments: 0

Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology. This white paper analyzes the impact of mat... » read more

Energy Analysis: 2D and 3D Architectures with Systolic Arrays and CIM (Cornell)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Energy-/Carbon-Aware Evaluation and Optimization of 3D IC Architecture with Digital Compute-in-Memory Designs" was published by researchers at Cornell University. "In this paper, we investigate digital CIM (DCIM) macros and various 3D architectures to find the opportunity of increased energy efficiency compared to 2D structures. Moreover, we also investigated th... » read more

Thermal Modeling For 2.5D And 3D Integrated Chiplets
By Technical Paper Link - 16 Oct, 2024 - Comments: 0

A new technical paper titled "MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures" was published by researchers at University of Wisconsin–Madison, Washington State University, and University of Ulsan. Abstract: "Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D d... » read more

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)
By Technical Paper Link - 27 Sep, 2024 - Comments: 0

A new technical paper titled "Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs" was published by researchers at imec. "We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous ... » read more

3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)
By Technical Paper Link - 12 Sep, 2024 - Comments: 0

A new technical paper titled "TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path" was published by researchers at Pohang University of Science and Technology and Baum Design Systems. Abstract "In the face of challenges posed by semiconductor scaling, 3D integration technology has emerged as a crucial solution to overcome the constraints of traditional 2D I... » read more

Enabling Efficient Multi-Die Design Implementation and IP Integration
By Synopsys - 28 Aug, 2024 - Comments: 0

Many industry trends are driving chip developers to consider multi-die designs using advanced 2.5D and 3D technologies. Such designs enable incorporating heterogeneous and homogeneous dies in a single package, increasing density while reducing signal propagation times. However, multi-die designs introduce new challenges that must be addressed by all relevant electronic design automation (EDA) a... » read more

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