tag: 3DIC

Energy Analysis: 2D and 3D Architectures with Systolic Arrays and CIM (Cornell)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Energy-/Carbon-Aware Evaluation and Optimization of 3D IC Architecture with Digital Compute-in-Memory Designs" was published by researchers at Cornell University. "In this paper, we investigate digital CIM (DCIM) macros and various 3D architectures to find the opportunity of increased energy efficiency compared to 2D structures. Moreover, we also investigated th... » read more

Thermal Modeling For 2.5D And 3D Integrated Chiplets
By Technical Paper Link - 16 Oct, 2024 - Comments: 0

A new technical paper titled "MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures" was published by researchers at University of Wisconsin–Madison, Washington State University, and University of Ulsan. Abstract: "Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D d... » read more

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)
By Technical Paper Link - 27 Sep, 2024 - Comments: 0

A new technical paper titled "Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs" was published by researchers at imec. "We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous ... » read more

3D IC Partitioning and Placement Method That Optimizes For Critical Paths (POSTECH)
By Technical Paper Link - 12 Sep, 2024 - Comments: 0

A new technical paper titled "TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path" was published by researchers at Pohang University of Science and Technology and Baum Design Systems. Abstract "In the face of challenges posed by semiconductor scaling, 3D integration technology has emerged as a crucial solution to overcome the constraints of traditional 2D I... » read more

Enabling Efficient Multi-Die Design Implementation and IP Integration
By Synopsys - 28 Aug, 2024 - Comments: 0

Many industry trends are driving chip developers to consider multi-die designs using advanced 2.5D and 3D technologies. Such designs enable incorporating heterogeneous and homogeneous dies in a single package, increasing density while reducing signal propagation times. However, multi-die designs introduce new challenges that must be addressed by all relevant electronic design automation (EDA) a... » read more

Heterogeneity Of 3DICs As A Security Vulnerability
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "Harnessing Heterogeneity for Targeted Attacks on 3-D ICs" was published by Drexel University. Abstract "As 3-D integrated circuits (ICs) increasingly pervade the microelectronics industry, the integration of heterogeneous components presents a unique challenge from a security perspective. To this end, an attack on a victim die of a multi-tiered heterogeneous 3-... » read more

Overview of Test Strategies for 3DICs
By Technical Paper Link - 26 Jun, 2024 - Comments: 0

A new technical paper titled "Design-for-Test Solutions for 3D Integrated Circuits" was published by researchers at Duke University, Arizona State University, and NVIDIA. Abstract: "As Moore's Law approaches its limits, 3D integrated circuits (ICs) have emerged as promising alternatives to conventional scaling methodologies. However, the benefits of 3D integration in terms of lower power co... » read more

Impact of Clustering Methods On Partitioning Decisions For 3DICs (imec, Université libre de Bruxelles)
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Impact of gate-level clustering on automated system partitioning of 3D-ICs” was published by researchers at Université libre de Bruxelles and imec. Abstract: "When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. ... » read more

3DICs: Legalizer Techniques For Better Routing Quality, Fewer DRVs, And Reduced Total Slack With Negligible Runtime Impact
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “On Legalization of Die Bonding Bumps and Pads for 3D ICs” was published by researchers at the Georgia Institute of Technology, NVIDIA Corporation, and the University of Bremen. Abstract "State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes and aggressive bonding pitch assumptions. As a result, these flows fail to honor the widt... » read more

3D-IC: Operator Learning Framework For Ultra-Fast 3D Chip Thermal Prediction Under Multiple Chip Design Configurations
By Technical Paper Link - 24 Mar, 2023 - Comments: 0

A new technical paper titled "DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design" was published (preprint) by researchers at UCSB and Cadence. Abstract "Thermal issue is a major concern in 3D integrated circuit (IC) design. Thermal optimization of 3D IC often requires massive expensive PDE simulations. Neural network-based thermal prediction models can perform ... » read more

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