Pandemics And Panic Chip Buying

By Mark LaPedus - 18 Jun, 2020 - Comments: 0

U.S.-China trade tensions are creating uncertainty in the semiconductor market, but it is also causing another event right now—panic chip buying. At present, some but not all foundry vendors are seeing “rush orders” for select products and are running their fabs at full capacity. It’s not just leading-edge devices, but also mature technologies. A surge of chip orders started in Ma... » read more

On-Chip Monitoring Of FinFETs

By Ed Sperling - 25 Jul, 2018 - Comments: 0

Stephen Crosher, CEO of Moortec, sat down with Semiconductor Engineering to discuss on-chip monitoring and its impact on power, security and reliability, including predictive maintenance. What follows are excerpts of that conversation. SE: What new problems are you seeing in design? Crosher: There are challenges emerging for companies working on advanced nodes, including scaling and trans... » read more

Better Chips, Better Cars

By Yan Qu - 16 Feb, 2017 - Comments: 0

There are literally thousands of electronic components in a new car, and those numbers are only going to increase as cars become smarter, safer, greener, and increasingly connected. As automakers and Tier 1 and Tier 2 companies shift their focus from mechanical to a combination of mechanical and electrical, there is an ongoing race among fabless companies to come up with innovative technolog... » read more

40nm Technology Reinvigorated

By Steve Sharp - 15 Dec, 2016 - Comments: 0

When selecting a foundry process for mobile consumer focused products, chip designers are considering the economics of the solution just as much as the technical specifications. Using the latest and greatest finFET process might get you performance headroom above your spec, but could cost significantly more than using a more established, proven process. Today’s 40nm CMOS processes have bee... » read more

Stepping Back From Scaling

By Ed Sperling - 24 Aug, 2016 - Comments: 0

Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry. While there is still demand from the largest chipmakers for increased density at the next process node, the underlying economics for foundries, equipment vendors and IP developers are f... » read more

Roots Of Distrust Spread

By Ed Sperling - 21 Jul, 2016 - Comments: 0

For most of the history of semiconductors there has been a persistent fear that someone would steal intellectual property from one company and sell it to another. There have been innumerable lawsuits involving corporate secrets that cross from one company to the next, and from one country to the next. The biggest concerns always were at the leading edges of technology, where those secrets w... » read more

Tech Talk: Lower Power Embedded NVM

By Ed Sperling - 12 Nov, 2015 - Comments: 0

Jen-Tai Hsu, Kilopass' vice president of engineering, talks about lower-voltage bit cells, where they fit in IoT designs and how they affect battery life. [youtube vid=dNDkuApHumU] » read more

Analog Evolves Into Mixed Signal

By Linh Hong - 06 Aug, 2015 - Comments: 0

Predictions about the Internet of Things suggest this may be the new “Killer App,” something the semiconductor industry has long been looking for. Reinforcing the forecasts are television commercials from companies such as Cisco and GE touting the IoT’s impact on everything from jet engines to robots, capturing everyone’s imagination. New categories of products such as smartwatches will... » read more

What’s Wrong With Power Signoff

By Ed Sperling - 12 May, 2014 - Comments: 0

Power signoff used to be a checklist item before a design went to tapeout. But as power has become a critical factor in designs, particularly at advanced nodes, signing off on power now needs to be done at multiple points throughout the design flow. That alone adds even greater complexity to already complex design processes because it requires fixed reference points and scenarios for taking mea... » read more

Litho Is Out Of Sync

By Ed Sperling - 20 Mar, 2014 - Comments: 0

EUV’s repeated missed deadlines, and the slow-motion response by the rest of the industry to fill the void with alternatives, is having ripple effects in every facet and corner of the semiconductor industry. It’s making design harder and more expensive, introducing potential errors into the DFM flow, and greatly increasing the amount of time it takes to process wafers. It’s also adding a ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

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by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.