Chip Ecosystem Apprenticeships Help Close The Talent Gap


Competency-based apprenticeship programs are gaining wider acceptance across the chip industry as companies and governments look for new ways to address talent shortages, and as workers look for new skills that can span multiple industry sectors and industries. Funded in part by the CHIPS Act in the U.S. the European Chips Act, and various other nation-specific and regional programs, apprent... » read more

Chip Industry Week In Review


By Jesse Allen, Linda Christensen, and Liz Allan.  The Biden administration plans to invest more than $5B  for semiconductor R&D and workforce support, including in the National Semiconductor Technology Center (NSTC), as part of the rollout of the CHIPS Act. Today's announcement included at least hundreds of millions for the NSTC workforce efforts, including creating a Workforce Cente... » read more

Blog Review: Feb. 7


Synopsys' Ian Land, Kenneth Larsen, and Rob Aitken find that a new approach will be required to ensure that higher volume 3D heterogeneous integration (3DHI) designs can function reliably and successfully in aerospace, defense, and government systems. Siemens' John Golding provides a primer on the fundamental concepts related to signal integrity, including key topics such as transmission lin... » read more

Software-Defined Vehicles Ready To Roll


Software-defined vehicles are driving a swell of activity across the automotive ecosystem, including new methodologies and technology approaches that could significantly reduce costs and shorten time to market for advanced features. The SDV approach encompasses more than a single concept. It helps to think of it more as a modeling approach that connects EVs, driver assistance technology, and... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan. Cadence introduced an AI-based thermal stress and analysis platform aimed at 2.5D and 3D-ICs, and cooling for PCBs and electronic assemblies. The company also debuted a HW/SW accelerated digital twin solution for multi-physics system design and analysis, combining GPU-resident computational fluid dynamics (CFD) solvers with dedicated GPU hardwar... » read more

Preparing For An AI-Driven Future In Chips


Experts at the Table: Semiconductor Engineering sat down to discuss the impact of AI on semiconductor architectures, tools, and security, with Michael Kurniawan, business strategy manager at Accenture; Kaushal Vora, senior director and head of business acceleration and ecosystem at Renesas Electronics; Paul Karazuba, vice president of marketing at Expedera; and Chowdary Yanamadala, technology s... » read more

Blog Review: Jan. 31


Synopsys' William Ruby argues for a comprehensive energy-efficient design methodology for automotive ICs as today's vehicles demand ever more computing power to support electrification, communication, and processing of massive amounts of data. Cadence's Mellacheruvu Srikanth finds that verifying all the new features and enhancements across several generations of PCIe while maintaining backwa... » read more

Blog Review: Jan. 24


Siemens' John McMillan finds that while 3D-IC capabilities are ready for mainstream, mass adoption success depends on how easily, effectively, and efficiently a solution can be delivered and points to five workflow adoption focus areas. Cadence's Andre Baguenie shows how to easily convert a logic signal to an electrical value using Verilog-AMS and the transition filter. Synopsys' Chris Cl... » read more

Blog Review: Jan. 17


Cadence's Rajneesh Chauhan introduces the Back-Invalidate feature in Compute Express Link (CXL) 3.0 and how it contributes to the efficient functioning of modern data center architectures by upholding cache coherence across multiple hosts and devices. Synopsys' Brett Murdock and Dana Neustadter point out the importance of protecting against DRAM attacks such as Rowhammer, RAMbleed, and cold-... » read more

SoC Telemetry & Performance Analysis Using Statistical Profiling Extension


The Arm Statistical Profiling Extension (SPE) is an architectural feature designed for enhanced instruction execution profiling within Arm CPUs. This feature has been available since the introduction of the Neoverse N1 CPU platform in 2019, along with performance monitor units (PMUs) generally available in Arm CPUs. An important step in extracting value from capabilities like SPE and PMUs is th... » read more

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