tag: ARM

Blog Review: November 29
By Jesse Allen - 29 Nov, 2023 - Comments: 0

Siemens' Matt Walsh checks out electro-thermal design and how a Boundary Condition Independent Reduced Order Model (BCI-ROM) can capture accurate characteristics from a 3D thermal analysis, ready for use in a 1D circuit simulation. Cadence's Vinod Khera considers how EDA could benefit from the AI revolution by providing a productivity boost through virtual assistants and improving code quali... » read more

Chip Industry Week In Review
By The SE Staff - 22 Nov, 2023 - Comments: 0

By Jesse Allen, Susan Rambo, and Liz Allan The U.S. government will invest about $3 billion for the National Advanced Packaging Manufacturing Program (NAPMP), including an advanced packaging piloting facility to help U.S. manufacturers adopt new technology and workforce training programs. It also will provide funding for projects concentrating on materials and substrates; equipment, tools, ... » read more

Chip Industry Week In Review
By The SE Staff - 17 Nov, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

Blog Review: November 15
By Jesse Allen - 15 Nov, 2023 - Comments: 0

Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

Flipping Processor Design On Its Head
By Ann Mutschler - 09 Nov, 2023 - Comments: 2

AI is changing processor design in fundamental ways, combining customized processing elements for specific AI workloads with more traditional processors for other tasks. But the tradeoffs are increasingly confusing, complex, and challenging to manage. For example, workloads can change faster than the time it takes to churn out customized designs. In addition, the AI-specific processes may ex... » read more

Neural Network Model Quantization On Mobile
By Roberto Lopez Mendez - 09 Nov, 2023 - Comments: 0

The general definition of quantization states that it is the process of mapping continuous infinite values to a smaller set of discrete finite values. In this blog, we will talk about quantization in the context of neural network (NN) models, as the process of reducing the precision of the weights, biases, and activations. Moving from floating-point representations to low-precision fixed intege... » read more

Blog Review: Nov. 8
By Jesse Allen - 08 Nov, 2023 - Comments: 0

Siemens' Todd Westerhoff takes a look at the three stages of power integrity analysis for PCBs, challenges to board-level signal integrity, and best practices for getting the most accurate estimate of design performance. Synopsys' William Ruby provides a brief overview of the evolution of low-power design techniques and finds opportunities to reduce power and to make chip designs more energy... » read more

For SDVs, Software Is The Biggest Challenge
By John Koon - 02 Nov, 2023 - Comments: 0

Software-defined vehicles (SDVs) involve far more than just OTA applications enabling software upgrades over the air. Software that will manage hundreds of ECUs and other functions within the vehicle is expected to grow beyond hundreds of millions of lines of code, possibly making SDV software development the number one challenge in automotive design. The benefits of SDVs, such as easy updat... » read more

Blog Review: November 1
By Jesse Allen - 01 Nov, 2023 - Comments: 0

Cadence’s Rich Chang finds that although UVM has being used for testbench creation for more than a decade, it is still challenging to debug problems that are inside of UVM testbench. Siemens’ Keith Felton suggests that early analysis in complex advanced packaging flows can enable designers to spot potential issues early to avoid built-in constructs that cause design failures and require ... » read more

What Will That Chip Cost?
By Brian Bailey - 30 Oct, 2023 - Comments: 1

In the past, analysts, consultants, and many other experts attempted to estimate the cost of a new chip implemented in the latest process technology. They concluded that by the 3nm node, only a few companies would be able to afford them — and by the time they got into the angstrom range, probably nobody would. Much has changed over the past few process nodes. Increasing numbers of startups... » read more

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