tag: Cadence

Keeping Security Algorithms Current Is Getting Harder
By Ann Mutschler - 04 Jun, 2026 - Comments: 0

Key Takeaways: Keeping security algorithms current is now a lifecycle challenge that spans chip design, manufacturing, deployment, and long-term maintenance across the supply chain. To stay ahead of emerging threats — especially post-quantum risks — hardware must be built with cryptographic agility, secure roots of trust, and reliable update mechanisms from the start. The bigge... » read more

AI-Defined Vehicles Increase Pressure On Auto Ethernet Reliability
By Liz Allan - 04 Jun, 2026 - Comments: 0

Key Takeaways: For AI-defined vehicles and onboard agentic AI, Automotive Ethernet provides high bandwidth for sensor data fusion, TSN ensures low latency and synchronization for real-time decisions, and MACsec secures the data link. Time-sensitive networking (TSN) is an essential protocol for ensuring 10BASE-T1S delivers data to where it needs to go on time. Still, it becomes less esse... » read more

Beyond PCIe Compliance: Why Stress Testing Is Crucial For Edge AI Deployments
By Joe Chen - 04 Jun, 2026 - Comments: 0

Passing PCI Express (PCIe) compliance is different from being ready for the field. A PCIe link can clear every test in a controlled lab environment and still develop margin problems six months into deployment. That’s because a compliance traffic generator isn’t designed to replicate real-world operating conditions, such as thermal stress, electrical noise, and the kind of bursty inference t... » read more

Blog Review: Jun. 3
By Jesse Allen - 03 Jun, 2026 - Comments: 0

Siemens' Gordon Allan contends that verification IP gives design teams a practical way to verify standards-based interfaces and memories without rebuilding the same infrastructure generation after generation and shares key evaluation metrics. Synopsys' Sutirtha Kabir suggests that successful multi-die design will require deeper collaboration from early architecture exploration to manufacturi... » read more

From Circuits to Systems: Unlocking the Power of Periodic Steady-State Analysis (eBook)
By Cadence - 03 Jun, 2026 - Comments: 0

RF and mixed-signal design verification is getting harder. Heterogeneous integration means sensitive RF blocks now sit next to noisy digital logic. Advanced-node CMOS means analog functions are increasingly implemented with fast-switching digital circuits. Wireless standards keep evolving, and the documentation runs hundreds of pages. Our new ebook, From Circuits to Systems: Unlocking the P... » read more

The Evolution Of UCIe
By Ed Sperling - 02 Jun, 2026 - Comments: 0

Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

Chip Industry Week In Review
By The SE Staff - 29 May, 2026 - Comments: 1

ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Swapping Out Chiplets: I/Os Vs. Compute
By Liz Allan - 28 May, 2026 - Comments: 0

Key Takeaways: Companies can save time and money by swapping out a compute, memory, or I/O chiplet to gain technology improvements, while keeping the other dies stable. Chip architects may choose to keep their I/Os stable and swap out compute to move from a 5nm process node to 3nm to achieve performance and power improvements, or swap out memory from LPDDR5X to LPDDR6. Swapping out... » read more

Toward Agentic Verification
By Brian Bailey - 28 May, 2026 - Comments: 1

Key Takeaways: Agentic verification provides flow orchestration for common repetitive tasks. Capabilities will expand when tools can learn from a larger context, including the specification. Design houses need to fully understand the costs and benefits and plan accordingly. Agentic verification is more than a buzzword. It is a pivotal moment in the evolution of verification ... » read more

Observability Is Essential For Modern Silicon
By Ann Mutschler - 28 May, 2026 - Comments: 0

Experts At The Table: In-silicon observability — also known as on-die or on-chip visibility — is becoming increasingly important for managing the performance, reliability, and security of today’s high-performance systems. Semiconductor Engineering sat down to discuss this with Andy Nightingale, vice president of product management and marketing at Arteris; Nandan Nayampally, chief commerc... » read more

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