tag: Cadence

A Scalable Answer To Advanced-Node Characterization
By Rajshekharayya Hiremath - 28 May, 2026 - Comments: 0

If you're working on standard-cell libraries at 28 nm or below, you already know the math isn't in your favor. At the 130 nm node, a typical library had fewer than 100 cells and a handful of PVT corners. Fast-forward to 16/14 nm and beyond, libraries now contain 1,200+ cells across 200+ PVT corners. Every new SoC tape-out demands broader coverage for design robustness, and the characte... » read more

Blog Review: May 27
By Jesse Allen - 27 May, 2026 - Comments: 0

Cadence's Igor Krause explains Precision Time Measurement (PTM), a PCIe feature that enables precise coordination of events across multiple components with independent local time clocks. Siemens' John McMillan suggests the way to achieve trusted traceability across the semiconductor supply chain is by implementing a blockchain-based distributed ledger paired with a secure digital twin. Sy... » read more

Chip Industry Week In Review
By The SE Staff - 22 May, 2026 - Comments: 0

Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Blog Review: May 20
By Jesse Allen - 20 May, 2026 - Comments: 0

Cadence's Siddh Virani demonstrates how to import and integrate foreign language logic into PSS on both Target and Solve platforms, opening possibilities for code reuse and cross-language collaboration. Synopsys' Sumit Vishwakarma finds that AI model training and inference workloads are forcing the industry to rethink not only how much compute fits in a rack, but how servers are architected ... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Chip Industry Week in Review
By The SE Staff - 15 May, 2026 - Comments: 0

Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

Structured Or Unstructured Meshes: What Works Best For Turbomachinery CFD
By Veena Parthan - 14 May, 2026 - Comments: 0

In computational fluid dynamics (CFD), meshing is a critical step for achieving reliable simulations, especially when combined with a robust solver strategy. As turbomachinery blade geometries become more intricate and design cycles shorten, traditional meshing approaches are often not enough. To keep pace, we must adopt advanced methodologies, and more importantly, quantify their impact on res... » read more

Gates Add Functionality, But Wires Create Problems
By Brian Bailey - 14 May, 2026 - Comments: 0

Key takeaways: While transistors see continuous improvement, wires keep getting worse because of the smaller geometries and larger chip sizes. There are limited ways to avoid such problems, but the biggest impact will come from floorplanning. Analysis today is not adequate. New developments, such as backside power and 3D integration, provide temporary relief but new materials are a d... » read more

Blog Review: May 13
By Jesse Allen - 13 May, 2026 - Comments: 0

Siemens' Loay Hegazy, Mohamed Taher, and Sherif Hammouda describe a GPU rasterizer designed specifically for computational lithography and present benchmark results and practical implications for mask synthesis workflows. Cadence's Udaya Shankar introduces RTL, logic, and physical restructuring techniques and how they can help improve PPA, reduce dynamic power consumption, and optimize place... » read more

Building AI Without Guardrails
By Ann Mutschler - 07 May, 2026 - Comments: 0

Key Takeaways: AI governance is broadly recognized as essential, but today it remains fragmented, largely aspirational, and lacking enforceable mechanisms for accountability, runtime assurance, and global interoperability. Because AI innovation is advancing too quickly for governments or standards bodies to keep pace, practical AI governance is most likely to emerge first from high‑ri... » read more

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