2.5D + 3D = “3.5D”!


The semiconductor industry is no longer defined solely by transistor scaling. As Moore's law decelerates, advanced packaging has become the primary lever for achieving system-level performance gains. Within this landscape, the equation 2.5D + 3D = 3.5D—defying the instincts of basic math and physics—captures a pivotal architectural evolution: one that balances performance, manufacturabilit... » read more

Humanoid Touch And Voice Are Improving Rapidly


Key Takeaways Humanoid robots are rapidly expanding beyond factories and logistics toward broader, general-purpose roles (including in-home assistance), driven by advances in AI and sensing. Compared with vision and language, touch (haptics) and hearing/voice in real environments remain the hardest — and most commercially important — sensing challenges, requiring fast sensor fusio... » read more

Blog Review: May 6


Synopsys' Prith Banerjee identifies key challenges in designing AI data centers and why addressing them requires a transformative approach that impacts every aspect of the system design and its individual components. Cadence's Meet S Chauhan checks out what's new in MIPI C-PHY v3.0, including the new 18 wire state mode that can support high-resolution display and image sensors and motion vec... » read more

Using AI To Monitor Dashboards In Chips And Systems


Key Takeaways: New types of dashboards are being used in conjunction with AI to make sense of large quantities of data. These dashboards can be used to quickly identify and fix power and heat-related problems, such as hotspots or voltage droop. Future dashboards will likely be much more customizable for different users or applications. Chipmakers are starting to use AI to ma... » read more

Designing Chips In The Context Of Rapidly Evolving AI


Key Takeaways: Agentic edge AI drives long-lived, tool-mediated loops with variable demands for compute, tokens, and memory. Edge PPA is dominated by memory hierarchy and data movement, forcing tight feature triage and robust RAS. Rapid model churn (multimodal, MoE, new formats) requires programmable, headroom-rich compute, interconnect, and runtime. Experts At The Table: Ch... » read more

Chip Industry Week in Review


Advanced nodes and capacity The US Commerce Dept. told IC equipment makers to stop shipments to Hua Hong Group, China's No. 2 chipmaker, in order to protect America's lead, according to Reuters. Global AI competition is causing wafer and packaging shortages, but capacity increases are expected to come online later this year and in 2027 to ease the crunch, according to TrendForce. Leadi... » read more

Creating Agentic EDA Methodologies


Key takeaways Agentic methodologies need to be able to reason across multiple data formats and abstractions. It is not clear how much data from previous designs is useful in new designs. Standards may help, but the lack of them may only impact cost. The relationship between tools and methodologies is bidirectional. Tools enable methodologies, and methodologies are dependent ... » read more

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes


Key Takeaways: Leading-edge node access is increasingly reserved for hyperscalers, squeezing smaller chip developers. Chiplets and advanced packaging offer a path forward, but raise cost, complexity, and risk — especially for smaller teams. Chip architecture is now driven as much by capacity, yield, and economics as by technical goals. The benefits of device scaling are sl... » read more

Unlocking High-Speed Serial Link Signal Integrity With AMI Model


As the demand for faster data rates in high-speed interfaces such as PCIe, USB, and DDR continues to escalate, maintaining signal integrity has become a significant challenge for engineers. Traditional SPICE-based simulations, while precise, often suffer from computational intensity, making it impractical to model the intricate behavior of high-speed signals across millions of bits. This is ... » read more

NoC Coherency Challenges Balloon With AI SoCs And Chiplets


Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

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