NoC Coherency Challenges Balloon With AI SoCs And Chiplets


Key Takeaways Data movement, congestion, and energy efficiency are key determiners of whether compute is usable. Different processors bring various coherency challenges. For example, a cache-coherent NoC for CPUs is expensive and harder to verify than an I/O-coherent NoC for an accelerator. Designers need to balance top-down performance with bottom-up physical engineering to effect... » read more

How Long Will CAN Stick Around As Rival Networks Speed Up?


Key Takeaways Automotive Ethernet is rapidly becoming the backbone of software-defined vehicles for higher bandwidth, scalability, and advanced features like TSN and security that legacy protocols cannot match. CAN, LIN, and other legacy networks will not disappear quickly because they are deeply embedded, low‑cost, and proven, but they are increasingly seen as inadequate for future A... » read more

Blog Review: Apr. 29


Synopsys' Madhumita Sanyal shows why interface IP has emerged as the keystone for building scalable, reliable 3D multi-die designs in which interconnects often have a greater influence on overall system capability than the peak performance of individual dies. Cadence's Frank Ferro checks out why SOCAMM2 built on LPDDR is being deployed in AI data centers, increasing memory bandwidth and capa... » read more

New CPU Memory Module


Moving data has become the top challenge inside data centers. There is more data to process, more to move, and more to store and retrieve from memory. This is where small outline compression attached memory modules (SOCAMMs) fit in. Frank Ferro, group director for product management at Cadence, talks about the benefits of this next-gen modular low-power memory standard, how it compares with oth... » read more

Chip Industry Week In Review


Deals Marvell acquired Polariton Technologies, a Swiss developer of plasmonics-based silicon photonics devices. Onto Innovation is partnering with Rigaku, combining Onto’s analysis software with Rigaku’s CD-SAXS platform for advanced semiconductor process control. Onto also agreed to acquire a 27% stake in Rigaku for about $710M. Tesla plans to use Intel’s 14A process for its T... » read more

Can Edge AI Keep Up?


Key Takeaways: Model development is outpacing silicon design cycles, so edge AI architectures must prioritize adaptability. The required cadence for model updates is highly application-dependent and is closely tied to product lifetime and operational risk. Adaptability can conflict with power, performance, and area targets, so effective heterogeneous architectures and robust softwa... » read more

Blog Review: Apr. 22


In a podcast, Siemens EDA's Harry Foster and Vladislav Palfy chat about why coverage closure has become one of the biggest bottlenecks in modern verification and how a unified approach that combines planning, automation, and analytics helps teams break through coverage plateaus. Synopsys' Emily Gerken and Marc Swinnen consider the challenges of designing analog and mixed-signal circuits at a... » read more

Batteries Charge To The Edge


Long-awaited advances in battery chemistry and materials science are beginning to roll out, opening the door for higher capacity, faster charging, and much lower likelihood of thermal runaway. This is a high-stakes race, fueled by an insatiable demand for power everywhere from handheld devices to data centers. When Finland's Donut Lab claimed earlier this year that it had developed a solid-s... » read more

Chip Industry Week In Review


Acquisitions and business pivots Teradyne acquired Israel-based TestInsight, a semiconductor test provider with pattern conversion, validation, and virtual test capabilities. Credo plans to acquire DustPhotonics, a developer of silicon photonics PICs for optical transceivers. Molex plans to acquire Teramount, a provider of detachable, passive-alignment fiber-to-chip connectivity solu... » read more

Chiplet Standards Aim For Plug-n-Play


Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

← Older posts Newer posts →