Blog Review: Apr. 22

In a podcast, Siemens EDA’s Harry Foster and Vladislav Palfy chat about why coverage closure has become one of the biggest bottlenecks in modern verification and how a unified approach that combines planning, automation, and analytics helps teams break through coverage plateaus.

Synopsys’ Emily Gerken and Marc Swinnen consider the challenges of designing analog and mixed-signal circuits at advanced nodes and why electromagnetic simulation is needed to extract accurate resistance, inductance, and capacitance or S-parameter models.

Cadence’s Sangeeta Soni finds that while CXL 4.0 takes a major leap forward in bandwidth, scalability, and system flexibility, it also introduces substantial verification complexity and suggests verification IP to reduce risk.

Keysight’s Doug Carson examines how physical access and operational design choices amplify risk and how ATM jackpotting attacks highlight a broader device security failure that extends well beyond the financial sector.

Arm’s Nick Dingle shares the latest updates to Arm Performance Libraries, including new sparse triangular solve functionality, more RNG distributions, reproducible math options in libamath, and performance gains across BLAS, LAPACK, and sparse routines.

SEMI’s Paul Carey and Rafael Tudela observe how sensors continue to evolve from simple sensing components to the essential “eyes and ears” of a global, AI-driven transformation.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

eBeam Initiative’s Jan Willis reviews the latest SPIE conference, finding that advances in GPU computing and multi-beam mask writing are removing constraints to enable entirely curvilinear masks.

Intel Foundry’s Han Wui Then and others demonstrate how to combine GaN transistors with silicon-based digital circuits to enable complex computing functions built directly into power chiplets.

Lam Research’s Swapnil Kailash More and Roopa Hegde show why small variations in mandrel and spacer dimensions can impact DRAM performance and yield.

Amkor Technology’s KyungSu Kim highlights a flip chip MLF packaging method that brings optimized signal paths, lower parasitics, and enhanced board-level thermal performance.

Synopsys’ Saurabh Suryavanshi discusses the importance of fine-tuning TCAD parameters with real-world feedback from test wafers to get quantitatively accurate and predictive results.

SEMI’s Rafael Tudela notes that achieving energy-efficient AI systems will require pre-competitive, industry-wide collaboration on foundational capabilities.