Blog Review: May 6

Synopsys’ Prith Banerjee identifies key challenges in designing AI data centers and why addressing them requires a transformative approach that impacts every aspect of the system design and its individual components.

Cadence’s Meet S Chauhan checks out what’s new in MIPI C-PHY v3.0, including the new 18 wire state mode that can support high-resolution display and image sensors and motion vector generators without adding more physical interconnects, and identifies key verification challenges.

Siemens’ Francisco Ezquerra Larrodé considers how AI has created rapid shifts in linguistics and finds the pattern mirrored in CFD, where PINNs, surrogates, and ROMs meant to accelerate simulation are fundamentally changing how the design process is conceptualized, the relationship between computation and experimentation, and the very nature of engineering analysis.

Intel Foundry’s Rao Desineni, Qian Liu, and Jonathan Byrne deploy an AI-enabled collaborative robot for automated routine inspection of interface test adapter pogo pins.

Keysight’s Yitian Ding explains how the optical behavior of waveguide combiners used in AR near-eye displays differs from conventional refractive systems and how k space analysis supports a structured workflow for diagnosing and mitigating stray light.

Arm’s Pascal Mudimba shows how hardware-level tuning helps optimize retrieval-augmented generation pipelines and how to confirm that math kernels use the hardware fully.

SEMI’s Serena Brischetto considers how Europe can forge a unified semiconductor strategy amidst geopolitical tensions, fast‑moving technological change, and ongoing supply‑chain challenges.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Vinci’s Satish Radhakrishnan looks at the challenges of isolated checkpoints for semiconductor design simulation.

Siemens EDA’s James Paris explains how to turn billions of DRC violations into actionable insights.

Cadence’s Priyadarshini N D examines the impact of integrating advanced equalization algorithms into channel simulations on eye diagrams, BER, and timing margins.

Arteris’ Andy Nightingale shows why the boundaries between IP reuse, interconnect design, and hardware-software integration are no longer independent.

Keysight EDA’s Maria Castillo points to design gaps in advanced package designs and what to do about them.

Synopsys’ Manoz Palaparthi finds traditional simulations lack an understanding of clocking requirements and cannot handle the complete clock network of a large chip.

Baya Systems’ Nandan Nayampally discusses the importance of scalable AMBA-compliant system connectivity.