UCIe And Automotive Electronics: Pioneering The Chiplet Revolution

By Vinod Khera - 09 May, 2024 - Comments: 0

The automotive industry stands at the brink of a profound transformation fueled by the relentless march of technological innovation. Gone are the days of the traditional, one-size-fits-all system-on-chip (SoC) design framework. Today, we are witnessing a paradigm shift towards a more modular approach that utilizes diverse chiplets, each optimized for specific functionalities. This evolution pro... » read more

Blog Review: May 8

By Jesse Allen - 08 May, 2024 - Comments: 0

Synopsys' Manuel Mota and Michael Posner look to UCIe as a complete stack for the die-to-die interconnect in multi-die chip designs, finding it can help maintain latency while reducing power and enhancing performance along with providing assurance of interoperability. Cadence's Durlov Khan highlights the Octal SPI interface for serial NAND flash, which enables 8-bit wide high bandwidth synch... » read more

CMOS Noise Margin Values

By Cadence - 08 May, 2024 - Comments: 0

One of the most important parameters describing digital systems operating at high speed is noise margin. In a general sense, noise margins define an acceptable level of noise that can be present on an I/O pin or in an interface. In terms of digital electronics, noise margin characterizes the level of noise that can appear on an I/O pin without creating an error in a received logic state. This i... » read more

Communication Is Key To Finding And Fixing Bugs In ICs

By Ann Mutschler and Adam Kovac - 08 May, 2024 - Comments: 0

Experts at the Table: Finding and eliminating bugs at the source can be painstaking work, but it also can prevent even greater problems from developing later on. To examine the best ways to tackle this problem, Semiconductor Engineering sat down with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager ... » read more

Fundamental Issues In Computer Vision Still Unresolved

By Karen Heyman - 02 May, 2024 - Comments: 1

Given computer vision’s place as the cornerstone of an increasing number of applications from ADAS to medical diagnosis and robotics, it is critical that its weak points be mitigated, such as the ability to identify corner cases or if algorithms are trained on shallow datasets. While well-known bloopers are often the result of human decisions, there are also fundamental technical issues that ... » read more

Design Considerations In Photonics

By Karen Heyman - 01 May, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about what CMOS and photonics engineers need to know to successfully collaborate, with James Pond, fellow at Ansys; Gilles Lamant, distinguished engineer at Cadence; and Mitch Heins, business development manager for photonic solutions at Synopsys. What follows are excerpts of that conversation. To view part one of this discussion,... » read more

Blog Review: May 1

By Jesse Allen - 01 May, 2024 - Comments: 0

Cadence's Vatsal Patel stresses the importance of having testing and training capabilities for high-bandwidth memory to prevent the entire SoC from becoming useless and points to key HBM DRAM test instructions through IEEE 1500. In a podcast, Siemens' Stephen V. Chavez chats with Anaya Vardya of American Standard Circuits about the growing significance of high density interconnect and Ultra ... » read more

Multi-Die Design Pushes Complexity To The Max

By Ann Mutschler - 29 Apr, 2024 - Comments: 1

Multi-die/multi-chiplet design has thrown a wrench into the ability to manage design complexity, driving up costs per transistor, straining market windows, and sending the entire chip industry scrambling for new tools and methodologies. For multiple decades, the entire semiconductor design ecosystem — from EDA and IP providers to foundries and equipment makers — has evolved with the assu... » read more

Chip Industry Week In Review

By The SE Staff - 26 Apr, 2024 - Comments: 0

President Biden announced four new Workforce Hubs to support the CHIPS Act and other initiatives, in Upstate New York, Michigan, Milwaukee, and Philadelphia. The White House also provided economic context and progress updates for the President’s workforce strategy. Samsung began mass production of its ninth-gen industry-first V-NAND chip. Along with one-terabit triple-level cell design, th... » read more

EDA Looks Beyond Chips

By Ed Sperling - 25 Apr, 2024 - Comments: 0

Large EDA companies are looking at huge new opportunities that reach well beyond semiconductors, combining large-scale multi-physics simulations with methodologies and tools that were developed for chips. Top EDA executives have been talking about expanding into adjacent markets for more than a decade, but the broader markets were largely closed to them. In fact, the only significant step in... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.