Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA

By Nayan Gaywala - 31 Oct, 2024 - Comments: 0

Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environme... » read more

Blog Review: Oct. 30

By Jesse Allen - 30 Oct, 2024 - Comments: 0

Synopsys' Frank Schirrmeister argues that hardware-assisted verification techniques like emulation and prototyping are essential to help engineers improve design behavior to manage complexity and ensure systems function seamlessly in real-world applications. Siemens’ Stephen V. Chavez finds that ultra high-density interconnect (UHDI) has changed the design and production of PCBs to enable ... » read more

Blog Review: Oct. 23

By Jesse Allen - 23 Oct, 2024 - Comments: 0

Cadence’s Sanjeet Kumar introduces the message bus interface in the PHY Interface for the PCIe, SATA, USB, DisplayPort, and USB4 Architectures (PIPE) specification, which provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires. Siemens’ Dennis Brophy argues that the recently published Portable Test and Stimulus Standard (PSS) 3.0 ... » read more

Chip Industry Week In Review

By The SE Staff - 18 Oct, 2024 - Comments: 0

Arm joined forces with Korea's Samsung Foundry, ADTechnology, and Rebellions to create a CPU chiplet platform for AI training and inference. The new chiplet will be based on Samsung's 2nm gate-all-around technology. Intel and AMD, arch competitors for decades, formed an x86 ecosystem advisory group to collaborate on architectural interoperability and simplify software development. Samsung... » read more

How Big A Deal Is Aging?

By Brian Bailey - 17 Oct, 2024 - Comments: 0

Nothing lasts forever, but in the semiconductor world things used to last long enough to become obsolete long before their end of life. That's no longer the case with newer nodes, and it is raising concerns in safety-critical markets such as automotive. Being able to fully understand what happens inside of chips is still a work in progress, and analysis approaches are trying to keep up. Unti... » read more

Is Liquid Cooling Right For Your Data Center?

By Mark Seymour - 17 Oct, 2024 - Comments: 0

We live in an exciting time—liquid cooling, which once seemed more trouble than it’s worth, is fast becoming an accepted and sought-after technology in the data center industry. That said, it’s still a complex technology to implement, especially in legacy facilities. Is your data center ready to operationalize liquid cooling? Liquid cooling in the data center Liquid cooling in the d... » read more

Mass Customization For AI Inference

By Ann Mutschler - 17 Oct, 2024 - Comments: 0

Rising complexity in AI models and an explosion in the number and variety of networks is leaving chipmakers torn between fixed-function acceleration and more programmable accelerators, and creating some novel approaches that include some of both. By all accounts, a general-purpose approach to AI processing is not meeting the grade. General-purpose processors are exactly that. They're not des... » read more

Data Center Digital Twin Return On Investment From An Environmental Standpoint

By Cadence - 16 Oct, 2024 - Comments: 0

Data center operators face growing pressure to enhance sustainability. Understanding where inefficiencies occur is the first step toward making impactful changes. Cadence Reality DC Digital Twin helps you identify inefficiencies, implement solutions, and track improvements. This white paper reveals how Cadence Reality DC Digital Twin can save an average of 316MWh annually, delivering a retur... » read more

Chip Industry Week In Review

By The SE Staff - 11 Oct, 2024 - Comments: 0

Imec announced a new automotive chiplet consortium to evaluate which different architectures and packaging technologies are best for automotive applications. Initial members includes Arm, ASE, Cadence, Siemens, Synopsys, Bosch, BMW, Tenstorrent, Valeo, and SiliconAuto. Imec also launched star, a global network bringing together automotive and semiconductor innovators to address technological c... » read more

Partial Header Encryption In Integrity And Data Encryption For PCIe

By Kunal Chhabriya - 10 Oct, 2024 - Comments: 0

Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols. Background Introducing PCIe's Integrity and Data Encryption Feature is an excell... » read more

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tag: Cadence

Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA

Blog Review: Oct. 30

Blog Review: Oct. 23

Chip Industry Week In Review

How Big A Deal Is Aging?

Is Liquid Cooling Right For Your Data Center?

Mass Customization For AI Inference

Data Center Digital Twin Return On Investment From An Environmental Standpoint

Chip Industry Week In Review

Partial Header Encryption In Integrity And Data Encryption For PCIe

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