Potential of Wireless Interconnects For Improving Performance And Flexibility Of Multi-Chip AI Accelerators


A new technical paper titled "Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators" was published by researchers at Universitat Politecnica de Catalunya. Abstract "The insatiable appetite of Artificial Intelligence (AI) workloads for computing power is pushing the industry to develop faster and more efficient accelerators. The rigidity of custom hardware, however, conflict... » read more

Automotive Outlook 2025: Ecosystem Pivots Around SDV


The automotive industry is deep in the throes of a massive shift to software-defined vehicle architectures, a multi-year effort that will change the way automotive chips are designed, where they are used, and how they are sourced. Creating a new vehicle architecture is no small feat. OEMs need to figure out who to partner with and which aspects of their current architecture to include. This ... » read more

Chiplets: Where Are We Today?


The 3rd annual Chiplet Summit was held in Santa Clara from January 21st to 23rd at the Convention Center. The conference continues to grow from its 1st year when it was held at the San Jose Doubletree Hotel (almost exactly 2 years ago). During his Chairman’s Welcome presentation, Chuck Sobey mentioned that there were 41 exhibitors at this year’s conference. Chuck was also the moderator f... » read more

Optimization of the Inter-Chiplet Interconnect And The Chiplet Placement (ETH Zurich, U. of Bologna)


A new technical paper titled "PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies" was published by researchers at ETH Zurich and University of Bologna. Abstract "2.5D integration technology is gaining traction as it copes with the exponentially growing design cost of modern integrated circuits. A crucial part of a 2.5D stacked chip is a low-latency and high-throughput inter-ch... » read more

UCIe For 1.6T Interconnects In Next-Gen I/O Chiplets For AI Data Centers


The rise of generative AI is pushing the limits of computing power and high-speed communication, posing serious challenges as it demands unprecedented workloads and resources. No single design can be optimized for the different classes of models – whether the focus is on compute, memory bandwidth, memory capacity, network bandwidth, latency sensitivity, or scale, all of which are affected by ... » read more

What’s Missing From Predictions


At this point everyone has made their predictions for the year, but there is one thing many people get wrong. Predictions are not about innovation. They are about pain and what is causing it. This industry is risk-averse, and everyone wants to continue doing what they are doing. But there comes a point when it's so painful to continue that something has to change. Having something that is... » read more

Chip Architectures Becoming Much More Complex With Chiplets


The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market. That hasn't dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors f... » read more

Chiplets Still A Challenge With UCIe 2.0


Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires. Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable s... » read more

Advanced Packaging Moving At Breakneck Pace


Experts at the Table: Semiconductor Engineering sat down to discuss advances in packaging with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. [Part 2 of the discussion is here.] ... » read more

Assembly Design Rules Slowly Emerge


Process design kits (PDKs) play an essential in ensuring that silicon technology can proceed from one generation to the next in a manner that design tools can keep up with. No such infrastructure has been needed for packaging in the past, but that's beginning to change with advanced packages. Heterogeneous assemblies are still ramping up, but their benefits are attracting new designs. “Chi... » read more

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