tag: DFT

Designing And Testing FinFET-based IC Designs
By Mentor Graphics Staff Writers - 19 Jun, 2014 - Comments: 0

By Carey Robertson and Steve Pateras The emergence of FinFET transistors has had a significant impact on the IC physical design and design-for-test flows. The introduction of FinFETs means that CMOS transistors must be modeled as three-dimensional (3D) devices during the IC design process, with all the complexity and uncertainty this entails. The BSIM Group of the UC Berkeley Device Group has ... » read more

Five Disruptive Test Technologies
By Mark LaPedus - 19 Jun, 2014 - Comments: 0

For years, test has been a critical part of the IC manufacturing flow. Chipmakers, OSATs and the test houses buy the latest testers and design-for-test (DFT) software tools in the market and for good reason. A plethora of unwanted field returns is not acceptable in today’s market. The next wave of complex chips may require more test coverage and test times. That could translate into higher... » read more

The Week In Review: Design
By Ed Sperling - 06 Jun, 2014 - Comments: 0

Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

Test Challenges Grow
By Mark LaPedus - 27 May, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: In our ... » read more

Drowning In Choices
By Ed Sperling - 15 May, 2014 - Comments: 0

There are at least half a dozen possible options for 28nm process technologies. There will be even more for the finFET generation. And that’s just the beginning of how complicated things will become over the next few years. There are multiple ways to test, seemingly infinite numbers of IP offerings—even from the same IP providers—and even more packaging options to put them together. Th... » read more

How Much Testing Is Enough?
By Mark LaPedus - 15 May, 2014 - Comments: 1

As chipmakers move towards finer geometries, IC designs are obviously becoming more complex and expensive. Given the enormous risks involved, chipmakers must ensure the quality of the parts before they go out the door. And as part of quality assurance process, that requires a sound test strategy. But for years, IC makers have faced the same dilemma. On one hand, they want a stringent test me... » read more

Test Challenges Grow
By Mark LaPedus - 15 May, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: What are... » read more

Divide And Conquer: Hierarchical DFT For SoC Designs
By Mentor, a Siemens Business - 14 May, 2014 - Comments: 0

Large System on Chip (SoC) designs present many challenges to all design disciplines, including design-for-test (DFT). By taking a divide-and-conquer approach to test, significant savings in tool runtime and memory consumption can be realized. This whitepaper describes the basic components of a hierarchical DFT methodology, the benefits that it provides, and the tool automation that is availabl... » read more

New Product Introduction Process For Heterogeneous 2.5D Devices
By Javier DeLaCruz - 28 Mar, 2014 - Comments: 0

For the past few years, the most popular topics in the 2.5D space have been: The design tools Foundry processes for through-silicon vias, temporary bonding and bump architecture The assembly process, such as what is first bonded to what The industry is at the point where the open variables on these topics are narrowing, and other critical aspects need to get far better attention. The... » read more

DFTMAX Compression Shared I/O
By Various Writers - 25 Jul, 2013 - Comments: 0

A significant design trend in recent years has been the widespread use of ARM multicore processors in systems-on-chip (SoCs). Designers’ ability to easily and cost-effectively employ multiple, high-performance embedded processors to meet the computational demands of the end application has helped fuel the explosive growth in mobile computing, networking infrastructure, and digital infotainmen... » read more

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