tag: DRAM

2022 Chip Forecast: Mixed Signals
By Mark LaPedus - 22 Feb, 2022 - Comments: 0

Jim Feldhan, president of Semico Research, sat down with Semiconductor Engineering to talk about the outlook for the semiconductor market. SE: What was your final 2021 semiconductor forecast? What is your 2022 semiconductor forecast? Feldhan: For 2021, world semiconductor revenues totaled $558 billion and units totaled over 1.1 trillion units. In terms of growth rate, revenues increased 2... » read more

SOT-MRAM To Challenge SRAM
By Bryon Moyer - 13 Jan, 2022 - Comments: 1

In an era of new non-volatile memory (NVM) technologies, yet another variation is poised to join the competition — a new version of MRAM called spin-orbit torque, or SOT-MRAM. What makes this one particularly interesting is the possibility that someday it could supplant SRAM arrays in systems-on-chip (SoCs) and other integrated circuits. The key advantages of SOT-MRAM technology are the pr... » read more

Reliability Concerns Shift Left Into Chip Design
By Ann Mutschler - 22 Dec, 2021 - Comments: 1

Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it's a way of offsetting rising design and manufacturing costs. What's changed is the new emphasis on solving these problems in the initial design. In the past, defectivity and yield were considered problems for the fab. Re... » read more

Covid Masks And Forecasts At Semicon
By Mark LaPedus - 16 Dec, 2021 - Comments: 0

Semicon West 2021 was certainty different, if not surreal, this year. The annual event was held in-person from Dec. 7-9, although there is a virtual component that runs until Jan. 7, 2022. In comparison, Semicon West was an all-virtual event in 2020, due to the Covid-19 pandemic. At this year’s in-person event in San Francisco, attendees, exhibitors and speakers were all required to wea... » read more

Understanding Electrical Line Resistance At Advanced Semiconductor Nodes
By Sandy Wen - 16 Dec, 2021 - Comments: 0

When evaluating shrinking metal linewidths in advanced semiconductor devices, bulk resistivity is not the sole materials property for deriving electrical resistance. At smaller line dimensions, local resistivity is dominated by grain boundary effects and surface scattering. Consequently, resistivity varies throughout a line, and resistance extraction needs to account for these secondary phenome... » read more

Scaling DDR5 RDIMMs To 5600 MT/s
By John Eble - 09 Dec, 2021 - Comments: 0

Looking forward to 2022, the first of the DDR5-based servers will hit the market with RDIMMs running at 4800 megatransfers per second (MT/s). This is a 50% increase in data rate over top-end 3200 MT/s DDR4 RDIMMs in current high-performance servers. DDR5 memory incorporates a number of innovations, such as Decision Feedback Equalization (DFE), and a new DIMM architecture which enable that speed... » read more

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
By Technical Paper Link - 18 Nov, 2021 - Comments: 0

Abstract "True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic primitives, scientific simulations, machine learning applications, and even recreational entertainment. Unfortunately, not every computing system is equipped with dedicated TRNG hardware, limiting the applicat... » read more

HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes
By Technical Paper Link - 18 Nov, 2021 - Comments: 0

Abstract: "State-of-the-art techniques for addressing scaling-related main memory errors identify and repair bits that are at risk of error from within the memory controller. Unfortunately, modern main memory chips internally use on-die error correcting codes (on-die ECC) that obfuscate the memory controller's view of errors, complicating the process of identifying at-risk bits (i.e., error pr... » read more

Outlook: DRAM, NAND, Next-Gen Memory
By Mark LaPedus - 18 Nov, 2021 - Comments: 0

Jim Handy, director at Objective Analysis, sat down with Semiconductor Engineering to talk about the 3D NAND, DRAM and next-generation memory markets. What follows are excerpts of that discussion. SE: How would you characterize the NAND market thus far in 2021? Handy: All chips are seeing unusual strength in 2021, but NAND flash and DRAM are doing what they usually do by exhibiting more e... » read more

Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications
By Technical Paper Link - 15 Nov, 2021 - Comments: 0

Abstract: "The RowHammer vulnerability in DRAM is a critical threat to system security. To protect against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips rely on undocumented, proprietary, on-die mitigations, commonly known as Target Row Refresh (TRR). At a high level, TRR detects and refreshes potential RowHammer-victim rows, but its exact are not openly disclose... » read more

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