tag: DRAM

LPDDR5X Opening New Markets For Low-Power DRAMs
By Shyam Sharma - 11 Apr, 2024 - Comments: 0

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market. This blog post talks about the evolutions of LPDDR DRAMs leading to the latest published standard of LPDDR5/5X. We also look at some of the traditional markets for LPDDR devices and how LPDDR5X is opening new specialized markets for the LPDDR DRAMs. History of LPDDR devices The first LPDDR standard,... » read more

Performance Boost In Powerful Real-Time Cortex-R Processor Using Data Prefetch Control
By Arm - 10 Apr, 2024 - Comments: 0

High-performance processors employ hardware data prefetching to reduce the negative performance impact of large main memory latencies. An effective prefetching mechanism can improve cache hit rate significantly. Data prefetching boosts the execution performance by fetching data before it is needed. While prefetching improves performance substantially on many programs, it can significantly red... » read more

Using Palladium To Address Contact Issues Of Buried Oxide Thin Film Transistors
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway" was published by researchers at Tokyo Institute of Technology and National Institute for Materials Science (NIMS). Abstract "Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures... » read more

Non-Destructive Metrology Techniques For Measuring Hole Profile In DRAM Storage Node
By Onto Innovation - 09 Apr, 2024 - Comments: 0

DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot... » read more

Rowhammer Exploitation On AMD Platforms, DDR4 DDR5 (ETH Zurich)
By Technical Paper Link - 03 Apr, 2024 - Comments: 0

A new technical paper titled "ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms" was published by researchers at ETH Zurich. The work will be presented at USENIX Security Symposium in August 2024. Abstract: "AMD has gained a significant market share in recent years with the introduction of the Zen microarchitecture. While there are many recent Rowhammer attacks launched from Intel CPU... » read more

Cache Coherency In Heterogeneous Systems
By Ed Sperling - 01 Apr, 2024 - Comments: 0

Until recently, coherency was something normally associated with DRAM. But as chip designs become increasingly heterogeneous, incorporating more and different types of compute elements, it becomes harder to maintain coherency in that data without taking a significant hit on performance and power. The basic problem is that not all compute elements fetch and share data at the same speed, and syst... » read more

DRAM Cache for GPUs With SCM And High Bandwidth
By Technical Paper Link - 26 Mar, 2024 - Comments: 0

A new technical paper titled "Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory" was published by researchers at POSTECH and Songsil University. Abstract "We propose overcoming the memory capacity limitation of GPUs with high-capacity Storage-Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity with SCM, the GPU can capture a larger fraction o... » read more

Designing AI Hardware To Deal With Increasingly Challenging Memory Wall (UC Berkeley)
By Technical Paper Link - 25 Mar, 2024 - Comments: 0

A new technical paper titled "AI and Memory Wall" was published by researchers at UC Berkeley, ICSI, and LBNL. Abstract "The availability of unprecedented unsupervised training data, along with neural scaling laws, has resulted in an unprecedented surge in model size and compute requirements for serving/training LLMs. However, the main performance bottleneck is increasingly shifting to memo... » read more

DRAM Chip Characterization Study of Spatial Variation of Read Disturbance and Future Solutions (ETH Zurich)
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich. Abstract: "Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used for breaking memory isolation, a fundamental building block for building robust systems. Row... » read more

The Rising Price Of Power In Chips
By Ed Sperling - 14 Mar, 2024 - Comments: 0

Power is everything when it comes to processing and storing data, and much of it isn't good. Power-related issues, particularly heat, dominate chip and system designs today, and those issues are widening and multiplying. Transistor density has reached a point where these tiny digital switches are generating more heat than can be removed through traditional means. That may sound manageable e... » read more

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