tag: DRAM

Semiconductor Metrology: IMMSE For The Rapid ID of Defective Chips (Samsung)
By Technical Paper Link - 05 Oct, 2025 - Comments: 0

A new technical paper titled "Ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry for semiconductor metrology" was published by researchers at Samsung. Abstract "We propose an ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry (IMMSE) system for semiconductor metrology. The IMMSE system achieves large-area measurements with a 20 mm × 20 mm field of ... » read more

Cost-Effective, Orthogonal Approach to Resilient Memory Design (Univ. of Central Florida, UT San Antonio, Rochester)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "SCREME: A Scalable Framework for Resilient Memory Design" was published by researchers at University of Central Florida, University of Texas at San Antonio and University of Rochester. Abstract "The continuing advancement of memory technology has not only fueled a surge in performance, but also substantially exacerbate reliability challenges. Traditional soluti... » read more

LPDDR: A Versatile Memory Powering The Next Wave Of Mobile, Edge & Endpoint Computing
By Raj Uppala - 11 Sep, 2025 - Comments: 0

The world of computing is evolving at a breakneck pace. From smartphones and ultra-thin laptops to autonomous vehicles and edge AI devices, the demand for memory that balances performance, power efficiency, and compact form factors has never been greater. This shift is driven by a few undeniable trends, including the increased deployment of AI models across verticals at the edge and higher us... » read more

HBM4 Memory: Break Through to Greater Bandwidth
By Rambus - 10 Sep, 2025 - Comments: 0

Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI training. HBM4 is the fourth major generation of the HBM standard, with new power management and RAS features. The Rambus HBM4 Controller provides industry-leading performance to 10.0 Gb/s, enabling a memory throughput of over 2.5 TB/s for training systems, generative AI and oth... » read more

The Evolution of DRAM
By Ed Sperling - 08 Sep, 2025 - Comments: 1

DRAM has been around since 1966, but today it's still the same basic 1T 1C bit cell architecture. Yet changes are coming as DRAM is called upon to store and retrieve more data faster. Steve Woo, distinguished inventor and fellow at Rambus, talks about how DRAM works, why there are different flavors, the impact of cooling new solutions in denser configurations, and ongoing issues involving the s... » read more

A Fundamental Rethinking Of Memory Hierarchy Design (Stanford University)
By Technical Paper Link - 05 Sep, 2025 - Comments: 0

A new technical paper titled "The Future of Memory: Limits and Opportunities" was published by researchers at Stanford University and an independent researcher. Abstract "Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large ... » read more

Tools, Models and System Support for PIM Architectures, With DRAM-Focus (ETH Zurich)
By Technical Paper Link - 04 Sep, 2025 - Comments: 0

A new technical paper titled "New Tools, Programming Models, and System Support for Processing-in-Memory Architectures" was published by researchers at ETH Zurich. Abstract "Our goal in this dissertation is to provide tools, programming models, and system support for PIM architectures (with a focus on DRAM-based solutions), to ease the adoption of PIM in current and future systems. To this ... » read more

Dynamic KV Cache Scheduling in Heterogeneous Memory Systems for LLM Inference (Rensselaer Polytechnic Institute, IBM)
By Technical Paper Link - 28 Aug, 2025 - Comments: 0

A new technical paper titled "Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System" was published by researchers at Rensselaer Polytechnic Institute and IBM. Abstract "Large Language Model (LLM) inference is increasingly constrained by memory bandwidth, with frequent access to the key-value (KV) cache dominating data movement. While attention sparsity red... » read more

Scaling DRAM Technology To Meet Future Demands: Challenges And Opportunities
By Rambus - 13 Aug, 2025 - Comments: 0

Since the invention of the 1T1C bit cell more than 50 years ago, DRAMs have become the main memory of choice for processors in computer systems and many consumer electronics devices. As new use computing paradigms have been created, including 3D graphics, cloud computing, smart phones, and AI processing, specialized processors and DRAM memories have been developed that are optimized for these u... » read more

LtRAM And StRAM: Specialized Memory Architectures Leveraging Workload-Specific Access Characteristics (Stanford, Microsoft)
By Technical Paper Link - 12 Aug, 2025 - Comments: 0

A new technical paper titled "Towards Memory Specialization: A Case for Long-Term and Short-Term RAM" was published by researchers at Stanford University and Microsoft, and an independent researcher. Abstract "Both SRAM and DRAM have stopped scaling: there is no technical roadmap to reduce their cost (per byte/GB). As a result, memory now dominates system cost. This paper argues for a parad... » read more

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