Accellera Preps New Standard For Clock-Domain Crossing

By Brian Bailey - 29 Feb, 2024 - Comments: 0

Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit. At the register transfer level (RTL), when a data signal passes between two flip flops, it initially is assumed that clocks are perfect. After clock-tree synthesis and place-and-route are perfor... » read more

What Happened To Portable Stimulus?

By Brian Bailey - 28 Sep, 2023 - Comments: 0

In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for a couple of decades. So what happened to it? Apart from a few updates at DVCon, there appears to be little talk about it today. However, the industry has its head down trying to make it work, ... » read more

Week In Review: Design, Low Power

By Linda Christensen - 17 Feb, 2023 - Comments: 0

It’s earnings season. Arm, Cadence, Synopsys, Siemens (consolidated), Rambus, and Renesas reported quarterly results over the past couple weeks. All posted year-over-year revenue growth, despite an overall challenging macroeconomic climate. A roundup of all the chip industry earnings reports from the past several weeks can be found here. The edge computing market is projected to jump to al... » read more

What Does 2023 Have In Store For Chip Design?

By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Scaling Simulation

By Brian Bailey - 27 May, 2021 - Comments: 1

Without functional simulation the semiconductor industry would not be where it is today, but some people in the industry contend it hasn't received the attention and research it deserves, causing a stagnation in performance. Others disagree, noting that design sizes have increased by orders of magnitude while design times have shrunk, pointing to simulation remaining a suitable tool for the job... » read more

Standards, Open Source, and Tools

By Brian Bailey - 10 May, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering discussed what open source verification means today and what it should evolve into with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardware engineer... » read more

An Industry Under Siege

By Ed Sperling - 05 Mar, 2020 - Comments: 0

The coronavirus is taking a big toll on the semiconductor industry's unquenchable thirst for new information. The longer it lasts, the more the industry will have to resort to technology — some new, some old — to continue moving forward. Over the past couple weeks, conferences and trade shows have been postponed or outright canceled. Synopsys, Cadence and Intel pulled out of DVCon at the... » read more

Abstracting Abstracter Abstractions In Functional Verification

By Neil Johnson - 26 Mar, 2018 - Comments: 0

I heard a clear three-part message during DVCon at the end of February: verification engineers must abstractly embrace the abstract idea of abstracting abstract abstraction through higher levels of abstraction; we overuse the word abstract to emphasize the value of whatever verification technique we happen to be talking about; and the key to new abstractions is using Portable Stimulu... » read more

Verification And Validation Brothers

By Brian Bailey - 22 Mar, 2018 - Comments: 0

At DVCon this year, Doug Amos took the stage for the [getentity id="22017" e_name="Mentor, a Siemens Business"] sponsored lunch presentation. For those of you who were there but decided to skip the lunch, expecting the traditional forced sales pitch, you made a mistake. Amos is one of those rare people who know how to inject humor, teaching and marketing into a single presentation such that the... » read more

The Week In Review: Design

By Jesse Allen - 23 Feb, 2018 - Comments: 0

Tools & IP Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.