tag: design for test

AI In Chip Manufacturing
By Ed Sperling - 10 Jan, 2019 - Comments: 0

Ira Leventhal, New Concept Product Initiative vice president at Advantest, talks with Semiconductor Engineering about using analysis and deep learning to make test more efficient and more effective. https://youtu.be/3VVG4JVnjHo » read more

Lab-To-Fab Testing
By Ed Sperling - 08 Oct, 2018 - Comments: 0

Test equipment vendors are working on integrating testing and simulation in the lab with testing done later in the fab, setting the stage for what potentially could be the most significant change in semiconductor test in years. If they are successful, this could greatly simplify design for test, which has become increasingly difficult as chips get more complex, denser, and as more heterogene... » read more

The Race To Zero Defects
By Jeff Dorsch - 10 Sep, 2018 - Comments: 1

By Jeff Dorsch and Ed Sperling Testing chips is becoming more difficult, more time-consuming, and much more critical—particularly as these chips end up in cars, industrial automation, and a variety of edge devices. Now the question is how to provide enough test coverage to ensure that chips will work as expected without slowing down the manufacturing process or driving up costs. Balanci... » read more

Changing The Design Flow
By Ed Sperling - 07 Aug, 2018 - Comments: 0

Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

Accelerating Test Pattern Bring-Up For Rapid First Silicon Debug
By Mentor, a Siemens Business - 12 Jul, 2018 - Comments: 0

Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially fo... » read more

Looking At Test Differently
By Ed Sperling - 05 Mar, 2018 - Comments: 1

Wilhelm Radermacher, executive advisor at [getentity id="22816" e_name="Advantest"], sat down with Semiconductor Engineering to discuss how the impact of rapid market changes, advanced packaging approaches and increasing complexity on test strategies and equipment. What follows are excerpts of that conversation. SE: As we move into new markets where use models and stresses on devices are dif... » read more

Tessent MissionMode: New Inline DFT Technology
By Mentor Graphics Staff Writers - 08 Jan, 2018 - Comments: 0

Written for automotive OEMs and suppliers, this whitepaper gives an overview of design-for-test (DFT) technology. Among the topics addressed: Why is DFT important in IC design generally and critical for creating automotive ICs in particular? And how does the new Tessent MissionMode technology, teamed with some of Mentor’s other DFT offerings, pave the way for the automotive industry to develo... » read more

Changes Ahead For Test
By Jeff Dorsch - 11 Dec, 2017 - Comments: 0

Testing microprocessors is becoming more difficult and more time consuming as these devices are designed to take on more complex tasks, such as accelerating artificial intelligence computing, enabling automated driving, and supporting deep neural networks. This is not just limited to microprocessors, either. Graphics processing units are grabbing market share in supercomputing and other area... » read more

The 2017 International Test Conference
By Jeff Dorsch - 09 Oct, 2017 - Comments: 0

Machine learning is a hot topic at many technical conferences this year. It will be true at the upcoming International Test Conference, which opens near the end of this month in Fort Worth, Texas. On Sunday, October 29, there are two tutorials devoted to machine learning. Monday, October 30, will have one tutorial related to the topic. The conference gets fully under way on Halloween, wit... » read more

Tech Talk: eFPGA Test
By Ed Sperling - 07 Sep, 2017 - Comments: 0

Volkan Oktem, director of product applications at Achronix, explains how to design a test approach for embedded FPGAs, including how to plan for sufficient coverage and how much it will cost. https://youtu.be/aGXd8QH-BfY   Related Stories Tech Talk: EFPGA Acceleration When and why to use embedded FPGAs. » read more

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