Cadence Cerebrus In SaaS And Imagination Technologies Case Study


Artificial Intelligence (AI) has made noteworthy progress and is now ready and available for electronic design automation. The Cadence Cerebrus Intelligent Chip Explorer utilizes AI—specifically, reinforcement machine learning (ML) technology—combined with the industry-leading Cadence digital full flow to deliver better power, performance, and area (PPA) more quickly. However, this highl... » read more

ESD Alliance And SEMI Efforts To Combat Design Automation Software Piracy


Piracy is a growing concern for all software providers, especially those of us with complex and specialized software, such as chip design automation software that is expensive to develop and maintain. That’s why the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, spearheaded an industry joint development effort to develop a server certification protocol that ... » read more

Optimizing Energy At The System Level


Power is a ubiquitous concern, and it is impossible to optimize a system's energy consumption without considering the system as a whole. Tremendous strides have been made in the optimization of a hardware implementation, but that is no longer enough. The complete system must be optimized. There are far reaching implications to this, some of which are driving the path toward domain-specific c... » read more

Changes And Challenges In Auto MCUs


Microcontrollers have been a key component in automotive for years, starting with single-core devices with limited on-chip memory for very basic functions, and evolving toward multi-core systems with more memory for more complex tasks. But as vehicles become increasingly automated, microcontrollers are changing significantly, and so is the perception of how to utilize them. These new devices ne... » read more

Design Tool Think Tank Required


When I was in the EDA industry as a technologist, there were three main parts to my role. The first was to tell customers about new technologies being developed and tool extensions that would be appearing in the next release. These were features they might find beneficial both in the projects they were undertaking today, and even more so, would apply to future projects. Second, I would try and ... » read more

Re-architecting Hardware For Energy


A lot of effort has gone into the power optimization of a system based on the RTL created, but that represents a small fraction of the possible power and energy that could be saved. The industry's desire to move to denser systems is being constrained by heat, so there is an increasing focus on re-architecting systems to reduce the energy consumed per useful function performed. Making signifi... » read more

Preparing For An AI-Driven Future In Chips


Experts at the Table: Semiconductor Engineering sat down to discuss the impact of AI on semiconductor architectures, tools, and security, with Michael Kurniawan, business strategy manager at Accenture; Kaushal Vora, senior director and head of business acceleration and ecosystem at Renesas Electronics; Paul Karazuba, vice president of marketing at Expedera; and Chowdary Yanamadala, technology s... » read more

EDA Back On Investors’ Radar


EDA is transforming from a staid but strategic sector into a hot investment market, fueled by strong earnings and growth, a clamoring for leading-edge and increasingly customized designs across new and existing markets, and the rollout of advanced technologies such as AI for a range of tools that will be needed to develop new architectures with much greater performance per watt. A confluence... » read more

Respect? Confused


In a recent story, I talked about how EDA has gained respect in the financial markets, which is something it has failed to do for decades. EDA, in the eyes of Wall Street, had become a plodder through good times and bad, failing to achieve the growth shown by semiconductor companies or foundries, or the rapid rise to glory of other software companies. Of course, it never experienced the same de... » read more

Fan-Out Panel-Level Packaging Hurdles


Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

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