tag: EUV

Week In Review: Manufacturing, Test
By Mark LaPedus - 19 Jun, 2020 - Comments: 0

Chipmakers and OEMs At next week’s Apple Worldwide Developers Conference, Apple is expected to roll out its long-awaited Arm-based Mac computers. This could provide a boost for Apple’s foundry vendor as well as equipment makers. It’s the worst-kept secret in the industry. As reported by the Apple sites, Apple is moving from Intel’s microprocessors to its own Arm-based chips for th... » read more

Interconnect Challenges Grow, Tools Lag
By Brian Bailey - 15 Jun, 2020 - Comments: 2

Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

Manufacturing Bits: June 8
By Mark LaPedus - 08 Jun, 2020 - Comments: 0

Maskless EUV lithography At this week’s 2020 EUVL Workshop, KJ Innovation will present more details about its efforts to develop a maskless extreme ultraviolet (EUV) lithography technology. Still in R&D, KJ Innovation’s maskless EUV technology involves a high-numerical aperture (high-NA) system with 2 million individual write beams. The 0.55 NA technology is targeted for direct-write l... » read more

Manufacturing Bits: June 2
By Mark LaPedus - 02 Jun, 2020 - Comments: 0

EUV lithography in outer space The U.S. space program made history on May 31, 2020, when NASA astronauts Robert Behnken and Douglas Hurley aboard SpaceX’s Crew Dragon spacecraft arrived at the International Space Station (ISS). This is the first time a commercial spacecraft has delivered astronauts to the ISS. The ISS serves as a research lab for companies, government agencies and universiti... » read more

EUV’s Uncertain Future At 3nm And Below
By Mark LaPedus - 21 May, 2020 - Comments: 5

Several foundries have moved extreme ultraviolet (EUV) lithography into production at both 7nm and 5nm, but now the industry is preparing for the next phase of the technology at 3nm and beyond. In R&D, the industry is developing new EUV scanners, masks and resists for the next nodes. 3nm is slated for 2022, followed by 2nm a year or two later. Nonetheless, it will require massive funding... » read more

Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
By Ed Sperling and Mark LaPedus - 21 May, 2020 - Comments: 0

Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

Consideration Of Missing Defect Suppression Technique In EUV Hole Patterning
By TEL - 21 May, 2020 - Comments: 0

This study focused on the defect behavior analysis with CD variation on EUV via hole pattern using photolithographic process and etch transfer performance. While defect requirements are not as stringent for memory devices, logic devices must be defect-free. Currently, a defect which comes from the process or material can only be detected by top-down inspection approach, however, it is difficult... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 17 Apr, 2020 - Comments: 0

Chipmakers TSMC posted mixed results for the quarter, although there was a capital spending surprise. “It maintained its 2020 capex at $15B-$16B despite smartphone softness, primarily to support a strong 5nm ramp, led by demand from 5G and HPC customers,” said Weston Twigg, an analyst at KeyBanc, in a research note. “Despite lowering its industry outlook, TSMC still expects to grow its o... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

The Impact Of EUV Resist Thickness On Via Patterning Uniformity
By Benjamin Vincent - 30 Mar, 2020 - Comments: 0

Via patterning at advanced nodes requires extremely low critical dimension (CD) values, typically below 30nm. Controlling these dimensions is a serious challenge, since there are many inherent sources of variation during lithography and etch processing. Coventor personnel, in conjunction with our colleagues from ASML and imec, recently looked at the impact of Extreme Ultraviolet lithography (EU... » read more

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