Can Nano-Patterning Save Moore’s Law?

By Mark LaPedus - 19 Nov, 2015 - Comments: 0

For years the academic community has explored a novel technology called selective deposition. Then, more than a year ago, Intel spearheaded an effort to bring the technology from the lab to the fab at 7nm or 5nm. Today, selective deposition is still in R&D, but it is gaining momentum in the industry. With R&D funding from Intel and others, selective deposition, sometimes called ALD-e... » read more

Inside Multi-Beam E-Beam Lithography

By Mark LaPedus - 19 Nov, 2015 - Comments: 4

Semiconductor Engineering sat down with David Lam, chairman of Multibeam, a developer of multi-beam e-beam tools for direct-write lithography applications. Lam is also a venture capitalist. He founded Lam Research in 1980, but left as an employee in 1985. What follows are excerpts of that conversation. SE: How has the equipment business changed over the years and what’s the state of the i... » read more

What’s Really Causing Line-Edge Roughness?

By Katherine Derbyshire - 19 Nov, 2015 - Comments: 0

As previously discussed, shot noise is an important contributor to line edge roughness. However, as the title of one paper on the subject put it, “Do not always blame the photons.” The line edge roughness of a chemically amplified resist ultimately depends on photoacid generation and the deprotection of the resist’s base monomers. Photons absorbed by the resist simply trigger a chain ... » read more

More Choices, Less Certainty

By Ed Sperling - 04 Nov, 2015 - Comments: 3

The increasing cost of feature scaling is splintering the chip market, injecting uncertainty into a global supply chain that has been continually fine-tuned for decades. Those with deep enough resources and a clear need for density will likely follow Moore's Law, at least until 7nm. What comes after that will depend on a variety of factors ranging from available lithography—EUV, multi-bea... » read more

The Next Resists

By Katherine Derbyshire - 22 Oct, 2015 - Comments: 5

As EUV exposure tools, sources, and photomasks have become more capable, the lithography sector’s attention has turned to EUV photoresist. After all, once the exposure system can produce a high quality image at the wafer, the resist still has to capture it for pattern transfer. Unfortunately, the increasing emphasis on photoresist has made the limitations of current formulations even more obv... » read more

Increasing Challenges At Advanced Nodes

By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

Taming Mask Metrology

By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

First Look: 5nm

By Ann Mutschler - 15 Oct, 2015 - Comments: 3

By the time the 5nm semiconductor manufacturing process node reaches mass production readiness, the hurdles and challenges will no longer be open for discussion. But as of this moment, some of them seem almost insurmountable, raising new questions about the continued viability of Moore's Law. There has been much written about the end of [getkc id="74" comment="Moore's Law"] for nearly two de... » read more

Gaps Remain For EUV Masks

By Mark LaPedus - 02 Oct, 2015 - Comments: 4

Extreme ultraviolet (EUV) lithography is once again at a critical juncture. The oft-delayed technology is now being targeted for 7nm. But there are still a number of technologies that must come together before EUV is inserted into mass production at that node. First, the EUV source must generate more power. Second, tool uptime must improve. Third, the industry needs better EUV resists. A... » read more

Resist Sensitivity, Source Power, And EUV Throughput

By Katherine Derbyshire - 30 Sep, 2015 - Comments: 0

In a recent article, I quoted 15 mJ/cm2 as the target sensitivity for EUV photoresists, and discussed the throughput that could be achieved at various source power levels. However, as a commenter on that article pointed out, reaching the 15 mJ/cm² target while also meeting line roughness requirements is itself a challenging problem. Because of the high energy of EUV photons, a highly sensitive... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?