tag: FPGA

FPGA-Based Prototyping Framework For Processing In DRAM (ETH Zurich & TOBB Univ.)
By Technical Paper Link - 10 Jan, 2023 - Comments: 0

A technical paper titled "PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM" was published by researchers at ETH Zurich and TOBB University of Economics and Technology. Abstract "Processing-using-memory (PuM) techniques leverage the analog operation of memory cells to perform computation. Several recent works have demonstrated PuM techniques in off-the-shelf DRAM dev... » read more

Integrating 16nm FPGA Into 28/22nm SoC Without Losing Speed Or Flexibility
By Geoff Tate - 05 Jan, 2023 - Comments: 0

Systems companies like FPGA because it gives parallel processing performance that can outdo processors for many workloads and because it can be reconfigured when standards, algorithms, protocols or customer requirements change. But FPGAs are big, burn a lot of power and are expensive. Customers would like to integrate them into their adjacent SoC if possible. Dozens of customers are now u... » read more

HW Accelerator Architecture for MI Computation With Low Latency, Energy Efficient (MIT)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A new technical paper titled "Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time" was published by researchers at MIT. Find the technical paper here. "In this paper, we introduce a new hardware accelerator architecture for MI computation that features a low-latency, energy-efficient MI compute core and an optimized memory subsystem that provides sufficie... » read more

A Full-Stack Domain-Specific Overlay Generation Framework Verified On FPGA
By Technical Paper Link - 12 Oct, 2022 - Comments: 0

A new technical paper titled "OverGen: Improving FPGA Usability through Domain-specific Overlay Generation" by researchers at UCLA and Chinese Academy of Sciences. "Our essential idea is to develop a hardware generation framework targeting a highly-customizable overlay, so that the abstraction gap can be lowered by tuning the design instance to applications of interest. We leverage and ext... » read more

Cybersecurity & FPGA Devices
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A technical paper titled "A Survey on FPGA Cybersecurity Design Strategies" is presented by researchers at Université Laval, Canada. Abstract (partial): "This paper presents a critical literature review on the security aspects of field programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. This paper also pays sp... » read more

Toward Domain-Specific EDA
By Brian Bailey - 26 Sep, 2022 - Comments: 0

More companies appear to be creating custom EDA tools, but it is not clear if this trend is accelerating and what it means for the mainstream EDA industry. Whenever there is change, there is opportunity. Change can come from new abstractions, new options for optimization, or new limitations that are imposed on a tool or flow. For example, the slowing of Moore's Law means that sufficient prog... » read more

Hardware Implementation Of A Random Gumber Generator On A FPGA
By Technical Paper Link - 13 Sep, 2022 - Comments: 0

A new research paper titled "FPGA Random Number Generator" was published by a researcher at Johns Hopkins University. According to the paper's abstract: "This paper offers a proof-of-concept for creating a verilog-based hardware design that utilizes random measurement and scrambling algorithms to generate 32-bit random synchronously with a single clock cycle on a field-programmable-gate-arr... » read more

Designing for FPGA Accelerators
By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This research paper titled "High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks" was published by researchers at Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy). According to the paper's abstract, "This paper presents a survey ... » read more

Fast and Flexible FPGA-based NoC Hybrid Emulation
By Technical Paper Link - 14 Jul, 2022 - Comments: 0

Researchers from RWTH Aachen University and Otto-von-Guericke Universitat Magdeburg have published a new technical paper titled "EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs." Abstract: "Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling co... » read more

SW/HW Framework for for GASNet-enabled FPGA Hardware Acceleration Infrastructure
By Technical Paper Link - 14 Jul, 2022 - Comments: 0

Researchers from KAIST and Flapmax published a new technical paper titled "FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration Infrastructure." Abstract "By providing highly efficient one-sided communication with globally shared memory space, Partitioned Global Address Space (PGAS) has become one of the most promising parallel computing model... » read more

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