Variables Complicate Safety-Critical Device Verification

By Ann Mutschler - 01 Jul, 2020 - Comments: 0

The inclusion of AI chips in automotive and increasingly in avionics has put a spotlight on advanced-node designs that can meet all of the ASIL-D requirements for temperature and stress. How should designers approach this task, particularly when these devices need to last longer than the applications? Semiconductor Engineering sat down to discuss these issues with Kurt Shuler, vice president of... » read more

Verdi Transaction Debug Platform: A Simplified Way To Debug IIP Designs And SoC

By Synopsys - 18 Dec, 2019 - Comments: 0

Authors: Abhishek Upadhyay, R&D Engineer, Synopsys, and Kanak Rajput, Application Engineer, Synopsys Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It’s not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the ... » read more

A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform

By Synopsys - 11 Dec, 2019 - Comments: 0

It's a longstanding cliche, but it is true that “there is no silver bullet for functional verification.” No single tool or methodology can find and shoot down all the bugs in a large, complex semiconductor design. Simulation is well understood but can be slow for today's large SoCs. Emulation hardware is fast, but expensive enough that it is usually shared across a verification team. Formal... » read more

SOC Design & IP Management—A Must For Functional Verification

By Cliosoft - 05 Jun, 2019 - Comments: 0

As a part of the verification flow, verification teams perform different types of simulations based on the nature of the design. The simulations include digital logic functional simulations, mixed-signal functional simulations, power-aware simulations, formal verification runs and gate-level simulations. For a signoff, all planned tests must pass in all four types of simulations. In addition t... » read more

Why IP Quality Is So Difficult To Determine

By Ann Mutschler - 30 May, 2019 - Comments: 0

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends up on how and where it is used and in part because even the best IP may work better in one system than another—even in chips developed by the same vendor. This has been one of the challenges with IP over the years. In many cases, IP is poorly characterized, regardless of whether that IP wa... » read more

Adding Order And Structure To Verification

By Brian Bailey - 30 May, 2019 - Comments: 0

You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal

By Sergio Marchese - 28 Mar, 2019 - Comments: 0

Time flies and the OneSpin’s Holiday Puzzle tradition has reached its third year. In December 2016, OneSpin challenged engineers everywhere to solve the Einstein riddle using assertions and a formal verification tool. In December 2017, the challenge was to model the hardest Sudoku in the world using assertions and find a solution with a formal tool. In addition, participants had to prove that... » read more

When Correct Is Not Enough: Formal Verification of Fault-Tolerant Hardware

By OneSpin Solutions - 27 Mar, 2019 - Comments: 0

Once upon a time, hardware functional verification was all about ensuring that a circuit would perform its specified functions under all legal input stimuli. Today, though, gaining confidence that a hardware design is correct is often not enough. Several industries, including automotive, medical, and aerospace, rely on safety-critical hardware to keep people safe. Other systems, for example, in... » read more

Portable Test and Stimulus Standard Version 1.0

By Accellera - 12 Dec, 2018 - Comments: 0

The definition of the language syntax, C++ library API, and accompanying semantics for the specification of verification intent and behaviors reusable across multiple target platforms and allowing for the automation of test generation is provided. This standard provides a declarative environment designed for abstract behavioral description using actions, their inputs, outputs, and resource depe... » read more

Domain Crossing Nightmares

By Brian Bailey - 27 Sep, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: functional verification

Variables Complicate Safety-Critical Device Verification

Verdi Transaction Debug Platform: A Simplified Way To Debug IIP Designs And SoC

A UFS Verification Closure Flow Using The Synopsys Verification Continuum Platform

SOC Design & IP Management—A Must For Functional Verification

Why IP Quality Is So Difficult To Determine

Adding Order And Structure To Verification

Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal

When Correct Is Not Enough: Formal Verification of Fault-Tolerant Hardware

Portable Test and Stimulus Standard Version 1.0

Domain Crossing Nightmares

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Top-Down Vs. Bottom-Up Chiplet Design

Knowledge Centers
Entities, people and technologies explored