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SOC Design & IP Management—A Must For Functional Verification

Learn the benefits of using a collaborative IP reuse ecosystem and design management platform for functional verification.

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As a part of the verification flow, verification teams perform different types of simulations based on the nature of the design. The simulations include digital logic functional simulations, mixed-signal functional simulations, power-aware simulations, formal verification runs and gate-level simulations.

For a signoff, all planned tests must pass in all four types of simulations. In addition to these functional and power test cases, designers must target performance use cases as well as code and functional coverage targets. Apart from these selected parts of the high risk logic is also subjected to exhaustive coverage using the formal verification.

When all this is coupled, with the continuously evolving specifications, bug fixes, numerous design handoffs between the milestones and the reliance of verification teams on various tools to complete the verification flow from concept to coverage sign-off, it becomes imperative to leverage SoC design and IP management solutions to seamlessly hold together the verification flow.

Not only do SoC design management solutions help manage the numerous revisions of all the documents and code, but they also enable design teams to work efficiently across multiple design sites spread across different geographical locations. IP management solutions on the other hand manage the various revisions of the IPs including the verification IPs, analog behavioral models and ensure that all team members are using the right revision of the IP for the project.

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