tag: IP

Die-to-Die Connectivity With High-Speed SerDes PHY IP
By Manuel Mota - 12 Mar, 2020 - Comments: 0

Hyperscale data center, artificial intelligence (AI), and networking SoCs have become more complex with advanced functionalities and have reached maximum reticle sizes. Designers are partitioning such SoCs in smaller modules requiring ultra- and extra-short reach links for inter-die connectivity with high data rates. The die-to-die connectivity must also ensure reliable links with extremely low... » read more

Power Management Becomes Top Issue Everywhere
By Ann Mutschler - 12 Mar, 2020 - Comments: 1

Power management is becoming a bigger challenge across a wide variety of applications, from consumer products such as televisions and set-top-boxes to large data centers, where the cost of cooling server racks to offset the impact of thermal dissipation can be enormous. Several years ago, low-power design was largely relegated to mobile devices that were dependent on a battery. Since then, i... » read more

Visualizing Differences In Analog Design
By Ed Sperling - 11 Mar, 2020 - Comments: 0

Prathna Sekar, technical account manager at ClioSoft, explains the challenges of managing analog versus digital IP, including how to deal with dozens or even hundreds of versions of a schematic, and why visualization is so important for identifying changes and updates to an analog design. » read more

The Cost Of Programmability
By Brian Bailey - 27 Feb, 2020 - Comments: 1

Nothing comes for free, and that is certainly true for the programmable elements in an SoC. But without them we are left with very specific devices that can only be used for one fixed application and cannot be updated. Few complex devices are created that do not have many layers of programmability, but the sizing of those capabilities is becoming more important than in the past. There are... » read more

Hybrid Prototyping
By Ed Sperling - 26 Feb, 2020 - Comments: 1

David Svensson, applications engineer in Synopsys’ Verification Group, explains how a virtual transaction logic model can be connected to develop hardware-dependent drivers before RTL actually exists, why this is now critical for large, complex designs, and how to find the potential bottlenecks and debug both software and hardware. » read more

Tracking Re-Use Of Design IPs
By Amit Varde - 24 Feb, 2020 - Comments: 0

Design teams have a great incentive to create design blocks or IPs that can be reused: Each time an IP is successfully reused, precious time is saved from project schedule. Of course, as easy as it sounds, achieving this goal in real life is not simple. In reality, the observation is that design libraries cannot be used as-is by multiple projects. Consider this scenario: A smart new graduate... » read more

What’s In Your IP?
By Ed Sperling - 21 Feb, 2020 - Comments: 0

Jeff Markham, software architect at ClioSoft, talks with Semiconductor Engineering about IP traceability in markets such as automotive and aerospace, what’s actually in IP, what should not be in that IP from a security standpoint, and how all of this data can used to avert system reliability issues in the future. » read more

Earlier Is Better In Latch-Up Detection
By Flint Yoder - 13 Feb, 2020 - Comments: 1

Physical verification is an essential step in integrated circuit (IC) design verification. Foundries provide design rule manuals that specify the precise physical requirements needed to ensure the design can be correctly manufactured, and the verification team runs the layout through checks based on those rules to ensure compliance. However, ensuring that a design can be manufactured does not g... » read more

Making Sure RISC-V Designs Work As Expected
By Ann Mutschler - 30 Jan, 2020 - Comments: 0

The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips. The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterization tends to be generalized, ra... » read more

Using Automotive IP For Easier Integration Of Safety Into SoCs
By Shivakumar Chonnad - 09 Jan, 2020 - Comments: 0

By Shivakumar Chonnad and Vladimir Litovtchenko Today’s SoCs for automotive safety-related systems integrate numerous IP blocks. At the system level, the Hardware Software Interface (HSI) between these IP blocks needs to be verified in simulation and validated in prototype. However, the scaling of the scope and effort to verify or validate is not linear based on the growing complexity of S... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy